Xia, Daxue. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references. / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

The rapid progress of n-type metal oxide thin film transistors (TFTs) has motivated research on p-type metal oxide TFTs in order to realise metal oxide-based CMOS circuits which enable low power consumption large-area electronics. Cuprous oxide (Cu2O) has previously been proposed as a suitable active layer for p-type metal oxide TFTs. The two most significant challenges for achieving good quality Cu2O TFTs are to overcome the low field-effect mobility and an unacceptably high off-state current that are a feature of devices that have been reported to date. This dissertation focuses on improving the carrier mobility, and identifying the main origins of the low field-effect mobility and high off-state current in Cu2O TFTs. This work has three major findings. The first major outcome is a demonstration that vacuum annealing can be used to improve the carrier mobility in Cu2O without phase conversion, such as oxidation (CuO) or oxide reduction (Cu). In order to allow an in-depth discussion on the main origins of the very low carrier mobility in as-deposited films and the mobility enhancement by annealing, a quantitative analysis of the relative dominance of the main conduction mechanisms (i.e. trap-limited and grain-boundary-limited conduction) is performed. This shows that the low carrier mobility of as-deposited Cu2O is due to significant grain-boundary-limited conduction. In contrast, after annealing, grain-boundary-limited conduction becomes insignificant due to a considerable reduction in the energy barrier height at grain boundaries, and therefore trap-limited conduction dominates. A further mobility improvement by an increase in annealing temperature is explained by a reduction in the effect of trap-limited conduction resulting from a decrease in tail state density. The second major outcome of this work is the observation that grain orientation ([111] or [100] direction) of sputter-deposited Cu2O can be varied by control of the incident ion-to-Cu flux ratio. Using this technique, a systematic investigation on the effect of grain orientation on carrier mobility in Cu2O thin films is presented, which shows that the [100] Cu2O grain orientation is more favourable for realising a high carrier mobility. In the third and final outcome of this thesis, the temperature dependence of the drain current as a function of gate voltage along with the C-V characteristics reveals that minority carriers (electrons) cause the high off-state current in Cu2O TFTs. In addition, it is observed that an abrupt lowering of the activation energy and pinning of the Fermi energy occur in the off-state, which is attributed to subgap states at 0.38 eV below the conduction band minimum. These findings provide readers with the understanding of the main origins of the low carrier mobility and high off-state current in Cu2O TFTs, and the future research direction for resolving these problems.

Zhao, Wei. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references. / Abstracts in English and Chinese. / Acknowledgements --- p.v / Chapter Chapter 1 --- Introduction --- p.1 / Chapter Chapter 2. --- H-bonded Acenes- An Approach to Self- assembled Organic Semiconductors --- p.16 / Chapter 2.1 --- Introduction --- p.16 / Chapter 2.2 --- Result and discussion --- p.17 / Chapter 2.3 --- Experiment --- p.23 / Chapter Chapter 3. --- Transistors from a Conjugated Macrocycle Molecule: Field and Photo Effects --- p.30 / Chapter 3.1 --- Introduction --- p.30 / Chapter 3.2 --- Result and discussion --- p.31 / Chapter 3.3 --- Conclusion --- p.37 / Chapter 3.4 --- Experiment --- p.37 / Chapter Chapter 4 --- Synthesis of Soluble and liquid crystalline Conjugated Macrocylces --- p.48 / Chapter 4.1 --- Introduction --- p.48 / Chapter 4.2 --- Result and Discussion --- p.49 / Chapter 4.3 --- Conclusion --- p.54 / Chapter 4.4 --- Experiment --- p.55 / Appendix --- p.65

Thesis (M. Phil.)--University of Hong Kong, 2006. / Title proper from title frame. Also available in printed format.

The long-term goal of this research project is the development of solution-based inorganic dielectric and semiconductor materials for inkjet printed electronics. The main focus of this thesis involves testing of the materials and devices under development. A new solution-based inorganic dielectric material (HfOSO₄), given the name hafsox, is developed and shows excellent dielectric properties. Hafsox with the addition of lanthanum, to improve film dehydration, has successfully been demonstrated as a gate dielectric. Metal-insulator-metal (MIM) capacitance testing of hafsox with lanthanum, has resulted in a low loss tangent of 0.30% at 1 kHz, a relative permittivity of 11.47 at 1 kHz, a breakdown voltage of 6.30 MV cm⁻¹, and a leakage current density of 4.38 nA cm⁻² at 1 MV cm⁻¹. Progress has also been achieved in the development of solution-based semiconductor materials. To date the most successful of these materials is zinc indium oxide (ZIO), which has been demonstrated as a thin-film-transistor (TFT) channel material. This ZIO TFT is a depletion-mode device with a turn-on-voltage of V[subscript on]~ -19 V, a threshold voltage of V[subscript T] ~-16 V, and a drain current on-to-off ratio of ~10³. Mobilities extracted from this ZIO TFT include an incremental mobility of μ[subscript inc] ~0.05 cm² V⁻' sec⁻', an effective mobility of μ[subscript eff] ~0.02 cm² V⁻' sec⁻', and an average mobility of μ[subscript avg] ~0.02 cm² V⁻' sec⁻' at V[subscript GS]=20 V. The development of metal-semiconductor field-effect transistors (MESFET) TFTs is also investigated as a means of eliminating the need for a dielectric material in order to reduce the complexity of fabricating circuits. MESFETs are attempted with semiconductor materials such as CdS that is deposited by chemical bath deposition (CBD) and SnO₂ that is deposited by RF magnetron sputtering, but with little success. The most successful MESFET-like device fabricated, employing SnO₂ as the channel material, is a strong depletion-mode device with a small amount of gate voltage modulation. / Graduation date: 2006

Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) are used as charge switches in flat-panel X-ray detectors. The inherent noise in the TFTs contributes to the overall noise figure of the detectors and degrades the image quality. Measurements of the noise provide an important parameter for modeling the performance of the detectors and are a sensitive diagnostic tool for device quality. Furthermore, understanding the origins of the noise could lead to change a method of a-Si:H deposition resulting in a reduction of the noise level. This thesis contains measurements of the low-frequency noise in a-Si:H TFTs with an inverted staggered structure. The noise power density spectrum fits well to a power law with Ñ near one. The normalized noise power is inversely proportional to gate voltage and also inversely proportional to channel length in both the linear and saturation regions. The noise is nearly independent of the drain-source voltage and drain-source current. The noise is unaffected by degrading the amorphous silicon through gate-biasing stress. Hooge¡¦s parameter is in the range 1-2*E-3 or 2-4*E-4 depending on whether the parameter is calculated using the total number of charge carriers in the accumulation layer or just the number of free carriers. As an example, the signal to noise ratio is calculated for photodiode detector gated by a TFT using the results from the noise measurements.

Increasing attention has been directed towards the development of optically transparent and mechanically flexible thin film transistors (TFTs) and associated circuits based on the transition metal oxides. These flexible see-through structures offer reduced weight, potential low-cost fabrication, and high performance compared to commonly used hydrogenated amorphous silicon (a-Si:H) in applications for large-area electronics and displays. As these emerging technologies evolve towards commercialization, a thorough investigation of the impacts of the thermo-mechanical stress and strain and their effects on the electrical and mechanical stability of the flexible microelectronic devices have become increasingly necessary. However, not much progress has been reported in this area, and the numerical modeling of the flexible transistors with the Finite Element Method (FEM) would provide unique insight to the design and operation of the flexible TFTs. In this thesis, numerical models of flexible TFTs are built up by COMSOL Multiphysics and compared with analytical models to reach the best agreement between the experimental measurements and the numerical analyses. These simulations provide additional insight into the local stress induced strain within the device due to both intrinsic and applied stress. It was shown that the thermal and mechanical impacts on the TFT performance can be reduced by placing the vital active layer of the flexible device near the neutral mechanical plane or by proper designing the device structure and processing conditions based on the data derived from the numerical models. The mathematical analysis and numerical simulation will be used to improve the electrical and mechanical performance and the reliability of the transistors for flexible applications.

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses. In our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity. Based on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time. Quantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric. Material and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

Thin film transistors (TFTs), the heart of highly functional and ultra-compact active-matrix (AM) backplanes, have driven explosive growth in both the variety and utility of large-area electronics over the past few decades. Nanocrystalline silicon (nc-Si:H) TFTs have recently attracted attention as a high-performance and low-cost alternative to existing amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) TFTs, in that they have the strong potentials which a-Si:H (low carrier mobility and poor device stability) and poly-Si (poor device uniformity and high manufacturing cost) counterparts do not have. However, the current nc-Si:H TFTs expose several challenging material and devices issues, on which the dissertation focuses. In our material study, the growth of gate-quality SiO2 films and highly conductive nc-Si:H contacts based on conventional plasma-enhanced chemical vapor deposition (PECVD) is systematically investigated, which can lead to high performance, reproducibility, predictability, and stability in the nc-Si:H TFTs. Particularly to overcome a low field effect mobility in the p-channel transistors, the possibility of B(CH3)3 as an alternative dopant source to current B2H6 is examined. The resultant p-doped nc-Si:H contacts demonstrate comparable performance to the state of the art with the maximum dark conductivity of 1.11 S/cm over 70% film crystallinity. Based on the highest-quality SiO2 and nc-Si:H contacts developed, complementary (n- and p-channel) top-gate nc-Si:H TFTs with a staggered source/drain geometry are designed, fabricated, and characterized. The n-channel TFTs demonstrate a threshold voltage VTn of 6.4 V, a field effect mobility of electrons μn of 15.54 cm2/Vs, a subthreshold slope S of 0.67 V/decade, and an on/off current ratio Ion/Ioff of 10^5, while the corresponding p-channel TFTs exhibit VTp of -26.2 V, μp of 0.24 cm2/Vs, S of 4.72 V/ decade, and Ion/Ioff of 10^4. However, the TFTs show significant non-ideal behaviors that considerably limit device performance: high leakage current in the off-state, transconductance degradation under high gate bias, and threshold voltage instability in time. Quantitative insight into each non-ideality is provided in this research. Our study on the off-state conduction in the nc-Si:H TFTs reveals that the responsible mechanism for high leakage current, particularly at a high bias regime, is largely due to Poole-Frenkel emission of trapped carriers in the reverse-biased drain depletion region. This could be effectively suppressed by proposed offset-gated structure without compromising the on-state performance. A numerical analysis of the transconductance degradation shows that the parasitic resistance components that are present in the nc-Si:H TFTs strongly degrade transconductance and thus a field effect mobility. Correspondingly, strategies for reduction in parasitic resistance of the TFT are presented. Lastly, the threshold voltage shift in the nc-Si:H TFT is attributed to the flatband voltage shift, which is mainly due to charge trapping in the PECVD SiO2 gate dielectric. Material and device study, and physical insight into non-ideal behaviors in the top-gate nc-Si:H TFTs reported in the dissertation constitute an arguably important step towards monolithic integration of pixels and peripheral driving circuits on a versatile active-matrix TFT backplane for high-performance and low-cost large-area electronics. However, the gate dielectric and the highly doped nc-Si:H contacts, still imposing considerable challenges, may require entirely new approaches.

Hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) are used as charge switches in flat-panel X-ray detectors. The inherent noise in the TFTs contributes to the overall noise figure of the detectors and degrades the image quality. Measurements of the noise provide an important parameter for modeling the performance of the detectors and are a sensitive diagnostic tool for device quality. Furthermore, understanding the origins of the noise could lead to change a method of a-Si:H deposition resulting in a reduction of the noise level. This thesis contains measurements of the low-frequency noise in a-Si:H TFTs with an inverted staggered structure. The noise power density spectrum fits well to a power law with Ñ near one. The normalized noise power is inversely proportional to gate voltage and also inversely proportional to channel length in both the linear and saturation regions. The noise is nearly independent of the drain-source voltage and drain-source current. The noise is unaffected by degrading the amorphous silicon through gate-biasing stress. Hooge¡¦s parameter is in the range 1-2*E-3 or 2-4*E-4 depending on whether the parameter is calculated using the total number of charge carriers in the accumulation layer or just the number of free carriers. As an example, the signal to noise ratio is calculated for photodiode detector gated by a TFT using the results from the noise measurements.