Because of the simple architecture and excellent error correcting capability, Turbo code has been adopted in many wireless communication standards, including the third generation wireless communication systems, 3GPP and 3GPP2. However, low power turbo decoder design would become the most important issue in mobile communication systems because of the limited battery life. In the thesis, we use the cyclic redundancy check (CRC) as the stopping criterion in the implementation of turbo decoder design to reduce the unnecessary power consumption. We use the MATLAB simulation and FPGA simulation to verify our design.

Design of low power Turbo decoder is one of the key issues in many modern communication systems such as 3 GPP. For the Turbo decoder architecture, the memory for the storage of the branch metric and state metric represents a major part of the entire decoder no matter in silicon area or power dissipation. Therefore, instead of saving the computed branch memory, this thesis adopts an alternative approach by saving the input in order to generate the branch memory on line. Furthermore, a novel design of state metric unit is proposed such that the size of the total state metric can be effectively reduced by a half with slightly overhead of adders/subtractors. For non-recursive systematic encoding applications, the same design methodology can further reduce the number of arithmetic units required in the soft-output calculating module. Our preliminary experimental result shows that the proposed design methodology can achieve 40% and 13% reduction on the gate count and power dissipation respectively.

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There are two important techniques, automatic repeat request (ARQ) and forward error control (FEC), in error control systems. ARQ uses redundancy for detecting errors. While an error is detected in a transmitted code word, the receiver requests the transmitter to re-transmit the corrupted code word and the transmitted code word with detected error is discarded. However, the transmitted code word with detected error still contains a lot of information. ARQ schemes require a feedback channel. FEC relies on the controlled use of redundancy in the transmitted code word to detect and correct errors. Whether the decoding of the received code word is successful, no further processing is performed at the receiver. Therefore, FEC requires only a one-way link between the transmitter and receiver. In error control systems, a powerful FEC, turbo coding, was first proposed in 1993. Its performance was investigated by simulation to be close to the Shannon limit. Hybrid ARQ (HARQ) systems after properly combining the ARQ techniques and FEC techniques, can be classified into type-I, type-II and type-III, and its performance can be elevated far more than ARQ systems. HARQ adopts the FEC methods to detect and correct the error patterns caused in the process of transmission. While errors are detected in the demodulated signals at receiver and fail to be corrected, the receiver will activate ARQ mechanism to request the transmitter to retransmit related information to achieve an error-free transmission. In this thesis, a feasible type-II hybrid ARQ algorithm is proposed. Performance of the proposed algorithm is evaluated and analyzed by computer simulations. Compared with the traditional HARQ algorithms, the proposed algorithm can offer better performance in delay time and number of retransmissions with approximate throughput.

This thesis studies advanced error control schemes using turbo-like codes, turbo-like coded modulations, turbo hybrid-ARQ (Automatic Repeat reQuest) schemes, and rate compatible puncturing techniques for reliable and adaptive commercial and tactical spread-spectrum communications, especially for code-division multiple access (CDMA) cellular systems and direct-sequence (DS) and frequency-hopping (FH) anti-jam systems. Furthermore, we utilize both the maximum-likelihood (ML) bounding techniques and convergence analysis to design and analyze various turbo-like coding schemes that show different behaviors in error performance from conventional trellis coding schemes. In the area of DS-CPM, we propose a DS concatenated coded CPM system for pulse-noise jamming channels and an anti-jam iterative receiver utilizing jammer state information. We also design a mixed concatenated CPM system that mixes CPM schemes with different convergence characteristics. In addition, we present the ML bound and convergence analysis for the jamming channel. In the area of FH-CPM, we propose anti-jam serially concatenated slow FH-CPM systems, whose phase is continuous during each hop interval, along with coherent and non-coherent iterative receivers. We also propose an iterative jamming estimation technique for the iterative receiver. In the area of multi-h CPM, we propose a power- and bandwidth-efficient serially concatenated multi-h CPM along with an appropriate iterative receiver structure. Serially concatenated multi-h CPM is shown to outperform single-h CPM. To design adaptive and versatile error control schemes using turbo-like codes for packet-data networks, we propose turbo hybrid-ARQ (HARQ) and rate compatible puncturing techniques for retransmission. In the area of turbo hybrid-ARQ, we propose a Type-I turbo HARQ scheme using a concatenated RS-turbo code and a packet combining technique for W-CDMA system to improve the performance of error and decoding latency. The W-CDMA system including the fast power control and coherent Rake receiver with a channel estimation technique for multipath fading channels is considered. Finally, in the area of rate compatible punctured turbo-like codes, we propose rate compatible punctured turbo (RCPT) codes and rate compatible punctured serially concatenated convolutional (RCPS) codes along with their puncturing methods. In addition, we propose Type-II RCPT-HARQ and RCPS-HARQ schemes to perform an efficient incremental redundancy retransmission.

Zugl.: Wuppertal, Univ., Diss., 2009

As the increasing demand for high data-rate multimedia servicesin wireless broadband access, the advance wireless communication technologies have been developed rapidly. The Long-Term Evolution (LTE) is the new standard for wireless broadband access recently specified by the 3GPP(3rd Generation Partnership Project) on the way towards the fourth-generation mobile. In this thesis, we are interested in the 3GPP-LTE technology and focus on the turbo coding technique used therein. By employing MATLAB/Simulink, we build up the turbo codec simulation platform for 3GPP-LTE system. Two convolutional encoders that realize the concept of parallel concatenated convolutional codes (PCCCs) and a quadratic permutation polynomial (QPP) interleaver are used to implement the turbo encoder. The a posteriori probability (APP) decoder built-in Simulink is utilized to design the decoder that performs the soft-input and soft-output Viterbi Algorithm (SOVA). The zero-order hold block is used to control the number of decoding iteration for the iterative decoding process. We carry out the 3GPP-LTE turbo codec performance in the AWGN channel on the developed platform. Various cases that consider different data length, the number of decoding iteration, interleaver and decoding algorithm are simulated. The simulation results are compared to those of the Xilinx 3GPP-LTE turbo codec. The comparisons show that our turbo codec works properly and meets the LTE standard.

Turbo Code, due to its excellent error correction capability, has been widely used in many modern wireless digital communication systems as well as data storage systems in recent years. However, because the decoding of the Turbo Code involves finding all the state probability and transition sequence, its hardware implementation is not straightforward as it requires a lot of memory and memory operation. In this thesis, a design of Turbo Code decoder IP (Intellectual Property) is proposed which can be parameterized with different word-lengths and code rates. The design of the core SISO (Soft-In Soft-Out) unit used in Turbo Code decoder is based on the algorithm of SOVA (Soft-Output Viterbi Algorithm). Based on the hybrid trace-back scheme, the SISO proposed in this thesis can achieve fast path searching and path memory reduction which can be up to 70% compared with the traditional trace-back approach. In addition, every iterative of Turbo Code decoding performs two SISO operations on the block of data with normal and interleaving order. In our proposed architecture, these two SISO operations can be implemented on a single SISO unit with only slightly control overhead. In order to improve the bit error rate performance, the threshold and normalization techniques are applied to our design. In addition, the termination criteria circuit is also included in our design such that the iteration cycle of the decoding can be reduced. The proposed Turbo Code decoder has been thoroughly tested and verified, and can be qualified as a robust IP.

No description available.

Dans cette thèse, nous nous intéressons au problème de la reconnaissance de code. Ce problème se produit principalement lorsqu'une communication est observée dans un milieu non-coopératif. Une liste de mots bruités issus d'un code inconnu est obtenue, l'objectif est alors de retrouver l'information contenue dans ces mots bruités. Pour cela, le code utilisé est reconstruit afin de décoder les mots observés. Nous considérons ici trois instances de ce problème et proposons pour chacune d'elle une nouvelle méthode. Dans la première, nous supposons que le code utilisé est un turbo-code et nous proposons une méthode pour reconstruire la permutation interne (les autres éléments du turbo-codeur pouvant être facilement reconstruits grâce aux méthodes existantes). Cette permutation est reconstruite pas à pas en recherchant l'indice le plus probable à chaque instant. Plus précisément, la probabilité de chaque indice est déterminée avec l'aide de l'algorithme de décodage BCJR. Dans la seconde, nous traitons le problème de la reconnaissance des codes LDPC en suggérant une nouvelle méthode pour retrouver une liste d'équations de parité de petits poids. Celle-ci généralise et améliore les méthodes existantes. Finalement, avec la dernière méthode, nous reconstruisons un code convolutif entrelacé. Cette méthode fait appel à la précédente pour retrouver une liste d'équations de parité satisfaites par le code entrelacé. Puis, en introduisant une représentation sous forme de graphe de l'intersection de ces équations de parité, nous retrouvons simultanément l'entrelaceur et le code convolutif. / In this PhD, we focus on the code reconstruction problem. This problem mainly arises in a non-cooperative context when a communication consisting of noisy codewords stemming from an unknown code is observed and its content has to be retrieved by recovering the code that is used for communicating and decoding with it the noisy codewords. We consider here three possible scenarios and suggest an original method for each case. In the first one, we assume that the code that is used is a turbo-code and we propose a method for reconstructing the associated interleaver (the other components of the turbo-code can be easily recovered by the existing methods). The interleaver is reconstructed step by step by searching for the most probable index at each time and by computing the relevant probabilities with the help of the BCJR decoding algorithm. In the second one, we tackle the problem of reconstructing LDPC codes by suggesting a new method for finding a list of parity-check equations of small weight that generalizes and improves upon all existing methods. Finally, in the last scenario we reconstruct an unknown interleaved convolutional code. In this method we used the previous one to find a list of parity-check equations for this code. Then, by introducing a graph representing how these parity-check equations intersect we recover at the same time the interleaver and the convolutional code.