<p>This work focuses on the surface and interfacial characterisation of silane films of a non-organofunctional silane, 1,2-bis(triethoxysilyl)ethane (BTSE), and an organofunctional silane, γ-mercaptopropyltrimethoxysilane (γ-MPS), deposited on Al, Zn and Al-43.4Zn-1.6Si (AlZn) alloy coated steel. Furthermore, a tribological study of a vegetable oil coupled to an aluminium surface pre-treated with γ-MPS is presented and, finally, the tribological response of thin organic coatings exposed to a sliding contact as evaluated by surface analysis is discussed. The main analyses techniques used were time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS). </p><p>The results presented in this thesis show that the combination of ToF-SIMS, AES and XPS analysis can be used in order to obtain useful and complementary information regarding the surface and interface characteristics of silane films and organic coatings deposited on metal substrates.</p><p>The major result regarding the silane films is that the silane film composition/structure is not dependent of pH-value during deposition or type of metal substrate. The presence of Si-O-Me ion fragments in the ToF-SIMS spectra is a strong indication that a chemical interaction between the silane film and the metal substrate exists. Furthermore, it has been shown that it is possible to bond a vegetable oil to a thiol functionalised aluminium surface and to produce a coating thick enough to obtain desired friction and wear characteristics. Finally, the use of ToF-SIMS analysis makes it possible to distinguish between mechanical and tribochemical wear mechanisms.</p>

This work focuses on the surface and interfacial characterisation of silane films of a non-organofunctional silane, 1,2-bis(triethoxysilyl)ethane (BTSE), and an organofunctional silane, γ-mercaptopropyltrimethoxysilane (γ-MPS), deposited on Al, Zn and Al-43.4Zn-1.6Si (AlZn) alloy coated steel. Furthermore, a tribological study of a vegetable oil coupled to an aluminium surface pre-treated with γ-MPS is presented and, finally, the tribological response of thin organic coatings exposed to a sliding contact as evaluated by surface analysis is discussed. The main analyses techniques used were time-of-flight secondary ion mass spectrometry (ToF-SIMS), Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS). The results presented in this thesis show that the combination of ToF-SIMS, AES and XPS analysis can be used in order to obtain useful and complementary information regarding the surface and interface characteristics of silane films and organic coatings deposited on metal substrates. The major result regarding the silane films is that the silane film composition/structure is not dependent of pH-value during deposition or type of metal substrate. The presence of Si-O-Me ion fragments in the ToF-SIMS spectra is a strong indication that a chemical interaction between the silane film and the metal substrate exists. Furthermore, it has been shown that it is possible to bond a vegetable oil to a thiol functionalised aluminium surface and to produce a coating thick enough to obtain desired friction and wear characteristics. Finally, the use of ToF-SIMS analysis makes it possible to distinguish between mechanical and tribochemical wear mechanisms.

Ce mémoire a trait à la nitruration du phosphure d'indium. Le phosphure d'indium est un semiconducteur III-V présentant un fort potentiel dans les domaines de la micro et de l'optoélectronique. La nitruration est un traitement de surface intervenant dans la croissance d'hétérostructures du type InN/InP.<br /> L'étude du processus de nitruration de l'InP(100) nécessite d'avoir une parfaite connaissance de l'état de la surface des substrats. Cette étude a été menée en employant différentes spectroscopies électroniques : spectroscopie des électrons Auger, des photoélectrons X, des pertes d'énergie des électrons et spectroscopie des électrons réfléchis élastiquement. Les effets du bombardement ionique -étape préalable à la nitruration- et du chauffage à une température égale à celle utilisée pour la nitruration ont été analysés. Le bombardement ionique entraîne la création de cristallites d'indium métallique qui subissent une transformation 3D-2D sous l'effet de la température.<br />La nitruration est réalisée dans un bâti ultravide. L'échantillon d'InP est exposé à un flux d'azote actif produit par une source à décharge haute tension. Les espèces azotées consomment les cristallites d'indium métallique précédemment créés par le bombardement ionique pour former de l'InN. Les effets du temps d'exposition au flux d'azote ainsi que de l'incidence du flux par rapport à la surface de l'échantillon ont été étudiés. Il s'est avéré que pour 40 minutes d'exposition sous une incidence rasante l'épaisseur des couches de nitrure était la plus importante. <br />L'étude d'un recuit des monocouches atomiques d'InN sur substrat d'InP à 450°C a montré le pouvoir passivant du film de nitrure puisque aucune détérioration du substrat n'a été constaté alors que la température de congruence de l'InP est de 370°C.

Phenol is highly reactive toward electrophilic aromatic substitution. By this general approach, many groups can be appended to the ring, via halogenation, acylation, sulfonation, and other processes. Phenol contains the hydroxyl group (–OH), which is a strongly activating ortho/para directing group in aromatic electrophilic substitution (AES). AES gives a mixture of ortho-and para isomers, which must be separated. The strong directing ability of phenol can also result in multiple substitutions on the aromatic ring which could be a major concern in the regiospecific synthesis of phenols. AES and Directed ortho--Metalation (DoM) are the only ways to directly substitute a proton on an aromatic ring and to synthesize regiospecifically substituted phenols. Phenol is a versatile precursor to a large collection of drugs, most notably aspirin, but also many herbicides and pharmaceuticals. AES reactions are useful in regiospecific synthesis as a way of introducing many reactive groups on the benzene ring and also help us to design a suitable method for synthesizing compounds in an efficient manner. Dimethylbenzylamine products are obtained as a result of the reaction of phenols with Eschenmoser’s salt (N,N-Dimethylmethyleneiminium iodide). This approach enables us to prepare regiospecifically ortho substituted phenols by using the AES protocol. We have discovered that Eschenmoser’s salt has the ability in basic medium containing triethylamine (TEA) to remove the proton and bond to the aromatic ring exclusively in ortho position to the –OH substituent. Our research work focused on efforts to render isolated products with minimum impurities, greener and more atom economical by use of limiting reagent in the reactions. For the purpose of evaluation of the obtained compounds and intermediates we use Gas Chromatography (GC), Gas Chromatography coupled with Mass Spectrometry (GC-MS) and Nuclear Magnetic Resonance (NMR). Our future work is to synthesize novel benzoheterocyclic compounds from the ortho-derivatised phenols as well as multi-substituted aromatic compounds. The dimethylamino methyl group can act as a directing group in the ortho-lithiation process; subsequent ortho--metalation and treatment with electrophiles generates 1,2,3- trisubstituted phenolic derivatives. Thus, phenolic precursors can be transformed into numerous derivatives which can be used in the chemical, agricultural and pharmaceutical industries.

The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data integrity is achieved by chaining Galois field multiplication operations while a symmetric key block cipher such as the Advanced Encryption Standard (AES), is used to meet goals of confidentiality. Area optimization in a number of proposed high throughput GCM designs have been approached through implementing efficient composite Sboxes for AES. Not as much work has been done in reducing area requirements of the Galois multiplication operation in the GCM which consists of up to 30% of the overall area using a bruteforce approach. Current pipelined implementations of GCM also have large key change latencies which potentially reduce the average throughput expected under traditional internet traffic conditions. This thesis aims to address these issues by presenting area efficient parallel multiplier designs for the GCM and provide an approach for achieving low latency key changes. The widely known Karatsuba parallel multiplier (KA) and the recently proposed Fan-Hasan multiplier (FH) were designed for the GCM and implemented on ASIC and FPGA architectures. This is the first time these multipliers have been compared with a practical implementation, and the FH multiplier showed note worthy improvements over the KA multiplier in terms of delay with similar area requirements. Using the composite Sbox, ASIC designs of GCM implemented with subquadratic multipliers are shown to have an area savings of up to 18%, without affecting the throughput, against designs using the brute force Mastrovito multiplier. For low delay LUT Sbox designs in GCM, although the subquadratic multipliers are a part of the critical path, implementations with the FH multiplier showed the highest efficiency in terms of area resources and throughput over all other designs. FPGA results similarly showed a significant reduction in the number of slices using subquadratic multipliers, and the highest throughput to date for FPGA implementations of GCM was also achieved. The proposed reduced latency key change design, which supports all key types of AES, showed a 20% improvement in average throughput over other GCM designs that do not use the same techniques. The GCM implementations provided in this thesis provide some of the most area efficient, yet high throughput designs to date.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

This thesis looked at three encryption applications that all use the symmetric encryption algorithms AES, Twofish and Serpent but differ in their implementation and how this difference would illustrate itself in performance benchmarks depending on the type of storage device that they were used on. Three mechanical hard drives and one solid state drive were used in the performance benchmarks which measured a variety of different disk operations across the three encryption applications and their algorithms. From the benchmarks performance charts were produced which showed that DiskCryptor had the best performance when using a solid state drive and that TrueCrypt had the best performance when using mechanical hard drives. By choosing DiskCryptor as the encryption application when using a solid state drive a performance increase of 38.9% compared to BestCrypt and 28.4% compared to TrueCrypt was achieve when using the AES algorithm. It was also shown that Twofish was overall the best performing algorithm. The primary conclusion that can be drawn from this thesis is that it is important to choose the right encryption application depending on the type of storage device used in order to get the best performance possible.

The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data integrity is achieved by chaining Galois field multiplication operations while a symmetric key block cipher such as the Advanced Encryption Standard (AES), is used to meet goals of confidentiality. Area optimization in a number of proposed high throughput GCM designs have been approached through implementing efficient composite Sboxes for AES. Not as much work has been done in reducing area requirements of the Galois multiplication operation in the GCM which consists of up to 30% of the overall area using a bruteforce approach. Current pipelined implementations of GCM also have large key change latencies which potentially reduce the average throughput expected under traditional internet traffic conditions. This thesis aims to address these issues by presenting area efficient parallel multiplier designs for the GCM and provide an approach for achieving low latency key changes. The widely known Karatsuba parallel multiplier (KA) and the recently proposed Fan-Hasan multiplier (FH) were designed for the GCM and implemented on ASIC and FPGA architectures. This is the first time these multipliers have been compared with a practical implementation, and the FH multiplier showed note worthy improvements over the KA multiplier in terms of delay with similar area requirements. Using the composite Sbox, ASIC designs of GCM implemented with subquadratic multipliers are shown to have an area savings of up to 18%, without affecting the throughput, against designs using the brute force Mastrovito multiplier. For low delay LUT Sbox designs in GCM, although the subquadratic multipliers are a part of the critical path, implementations with the FH multiplier showed the highest efficiency in terms of area resources and throughput over all other designs. FPGA results similarly showed a significant reduction in the number of slices using subquadratic multipliers, and the highest throughput to date for FPGA implementations of GCM was also achieved. The proposed reduced latency key change design, which supports all key types of AES, showed a 20% improvement in average throughput over other GCM designs that do not use the same techniques. The GCM implementations provided in this thesis provide some of the most area efficient, yet high throughput designs to date.

The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher was found to reduce its dynamic power consumption by up to 17% when compared to an identical design that did not employ the technique.

This thesis study presents design and SystemC implementation of a Crypto Processor for Advanced Encryption Standard (AES), Data Encryption Standard (DES) and Triple DES (TDES) algorithms. All of the algorithms are implemented in single architecture instead of using separate architectures for each of the algorithm. There is an Instruction Set Architecture (ISA) implemented for this Crypto Processor and the encryption and decryption of algorithms can be performed by using the proper instructions in the ISA. A permutation module is added to perform bit permutation operations, in addition to some basic structures of general purpose micro processors. Also the Arithmetic Logic Unit (ALU) structure is modified to process some crypto algorithm-specific operations. The design of the proposed architecture is studied using SystemC. The architecture is implemented in modules by using the advantages of SystemC in modular structures. The simulation results from SystemC are analyzed to verify the proposed design. The instruction sets to implement the crypto algorithms are presented and a detailed hardware synthesis study has been carried out using the tool called SystemCrafter.