This thesis aims to implement a linear wireless transmitter based on the envelope-following architecture. A class-E PA is utilized to replace the linear PA used in the traditional envelope-following transmitter for enhancing the average efficiency. The transmitter relies on a digital processor realized by FPGA to generate the baseband IQ signal and corresponding envelope signal. This way can not only achieve more accurate modulation accuracy and wider modulation bandwidth, but also use less analog components for the future convenience of realizing single-chip integration when compared to the traditional envelope-following transmitter. Furthermore, this thesis implements a predistorter in the digital processor to compensate the Vdd/AM distortion of class-E amplifier. Therefore, this transmitter can simultaneously achieve high efficiency and high linearity over a wide input power range. From the results measured in transmitting a QPSK-modulated CDMA2000 1x signal at a chip rate of 1.2288 Mcps, the transmitter incorporating an InGaAs pHEMT class-E PA can achieve 30~44 % in average efficiency (23~38 % in average PAE) with above 44 dBc in ACPR and below 4 % in EVM in the average modulated output power range from 7 to 21 dBm, while the transmitter incorporating a GaAs HBT can achieve 20~40 % in average efficiency (16~35 % in average PAE) with above 43 dBc in ACPR and below 5 % in EVM in the average modulated output power range from 4 to 18.5 dBm.

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