Walls encasing equivalent modules of space form a structure visually connecting individual elements into a single organism. The placement and form of these walls allows each module of space to retain distinct lighting qualities conversely drawing the individual out of the whole. / Master of Architecture

Cette thèse porte sur le thème général de la fiabilité des circuits microélectroniques. Le but de notre travail fut de développer un outil de simulation multi-physiques pour la conception des circuits intégrés fiables qui possède les caractéristiques innovatrices suivantes : • (i) L’intégration dans un environnement de conception microélectronique standard, tel que l’environnement Cadence® ; • (ii) La possibilité de simulation, sur de longues durées, du comportement des circuits CMOS analogiques en tenant compte du phénomène de vieillissement ; • (iii) La simulation de plusieurs physiques (électrique-thermique-mécanique) couplées dans ce même environnement de CAO en utilisant la méthode de simulation directe. Ce travail de thèse a été réalisé en passant par trois grandes étapes traduites par les trois parties de ce manuscrit. / This thesis was carried out under the theme of the microelectronics Integrated Circuits Reliability. The aim of our work was to develop a multi-physics simulation tool for the design of reliable integrated circuits. This tool has the following innovative features : • (i) The integration in a standard microelectronics design environment, such as the Cadence® environment ;• (ii) The possibility of efficient simulation, over long periods, of analog CMOS circuits taking into account the aging henomenon ; • (iii) The simulation of multiple physical behaviours of ICs (electrical-thermalmechanical) coupled in the same environment using the direct simulation method. This work was carried out through three main stages detailed in the three parts of this Manuscript.

The resolution of CMOS image sensor is becoming higher and higher, while for identifying its performance, designers need to do a series of simulations, and this work consumes large CPU time in classical design environment. This thesis titled "Fast Scalable and Variability Aware CMOS Image Sensor Simulation Methodology" is dedicated to explore a new simulation methodology for improving the simulation capability. This simulation methodology is used to study the image sensor performance versus low level design parameter, such as transistor size and process variability. The simulation methodology achieves error less than 0.4% on 3T-APS architecture. The methodology is tested in various pixel architectures, and it is used in simulating image sensor with 15 million pixels, the simulation capability is improved 64 times and time consumption is reduced from days to minutes. The potential application includes simulating array-based circuit, such as memory circuit matrix simulation.

Le bruit de combustion est devenu un contributeur de plus en plus important dans le bruit total de moteur d'avion. Ce bruit global a deux composantes: Le bruit direct et le bruit indirect. Le premier est issu des fluctuations de dégagement de chaleur dans la flamme elle-même. Le deuxième a pour origine les inhomogénéités de température dans les gaz brûlés. L'objectif de ce travail est la conception d'un banc de combustion sous pression avec une flamme pauvre, prémélangée swirlée dont les paramètres d'injection permettront d'obtenir des grandes quantités de bruit indirect.Il est nécessaire de caractériser ce banc et d'établir quelle est la part du bruit direct et de l'indirect afin d'identifier les sources de ces contributions. Pour cette caractérisation il est nécessaire d'utiliser différents diagnostics, de prendre en compte la résolution temporelle. Ces diagnostics à haute cadence permettent de caractériser les champs de vitesse et les dynamiques de flamme, les instabilités de combustion dans le système et ainsi évaluer les contributions du bruit direct et indirect. / Combustion noise has become an increasing contributor of overall aircraft engine noise. It consists of two major parts, direct and indirect combustion noise. The former is generated by the heat release fluctuations of the flame itself. The latter is generated by the temperature inhomogeneities in the burnt gases, which are accelerated in the turbine stages or nozzle following the combustion chamber.The aim of this work is to design and build a pressurized lean swirling combustor test bench, in order to quantify the two contributions.The combustor is thus supposed to generate high quantities of indirect combustion noise. The second aim is then to determine the contributions of direct and indirect combustion noise quantitatively and to gain insight about the sources of the two contributions. These analyses are conducted by different high-speed diagnostics, which were worked on during this work. These diagnostics allow to characterize the flow fields and flame dynamics, to put forward the combustion instability in the system and finally to quantify the direct and indirect combustion noise contributions.

<p>Multiplikatorer används ofta som ett byggblock vid konstruktion av kretsar som digitala filter, FFT-processorer och aritmetiska enheter. Olika trädstrukturer används i"höghastighet"applikationer för multiplikatorer. En typ av träd,"overturned-stairs"(OS) som är ett adderarträd av första ordningen har uppvisat lika optimal prestanda med avseende på hastighet som Wallace-träd, vid 18 eller färre ingångar. I moderna integrerade kretsar, ger ledningar och kopplingar upphov till fördröjningar och parasitiska laster. I en jämförelse mellan Wallace-träd, och OS1-träd har det sistnämda kortare och mindre komplicerad ledningsdragningar och är därför mer ändamålsenlig för VLSI implementationer.</p>

<p>A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application.</p><p>These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area.</p><p>The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction.</p><p>The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.</p>

Multiplikatorer används ofta som ett byggblock vid konstruktion av kretsar som digitala filter, FFT-processorer och aritmetiska enheter. Olika trädstrukturer används i"höghastighet"applikationer för multiplikatorer. En typ av träd,"overturned-stairs"(OS) som är ett adderarträd av första ordningen har uppvisat lika optimal prestanda med avseende på hastighet som Wallace-träd, vid 18 eller färre ingångar. I moderna integrerade kretsar, ger ledningar och kopplingar upphov till fördröjningar och parasitiska laster. I en jämförelse mellan Wallace-träd, och OS1-träd har det sistnämda kortare och mindre komplicerad ledningsdragningar och är därför mer ändamålsenlig för VLSI implementationer.

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also becomes quite important as more area means more system cost. Speed is another key parameter while designing a multiplier for a specific application. These three parameters i.e. power, area and speed are always traded off. Speaking of DSP processors, area and speed of MAC unit are the most important factors. But sometimes, increasing speed also increases the power consumption, so there is an upper bound of speed for a given power criteria. Considering the battery operated portable multimedia devices, low power and fast designs of multipliers are more important than area. The design of a low power, high speed and area efficient multiplier is thus the goal of my thesis work. The projected plan is to instantiate a good design and modify it for low power and speed and prepare its layout using 90nm technology in Cadence®. For that purpose study has been performed on a number of research papers presented in section 7 and selected one of the architecture presented by Jung-Yup Kang and Jean-Luc Gaudiot. They presented a unique technique for power reduction in Wallace tree multipliers. They have proposed a method to calculate 2’s complement of multiplicand for final Partial Product Row (PPR) if using MBE technique. This method has been used in the design for speed enhancement and power reduction. The ultimate purpose is to come up with such an architecture which is energy and area efficient than a conventional multiplier at the same performance level. This report describes the design and evaluation of new energy-efficient 32-bit multiplier architecture by comparing its power, performance and chip area to those of a conventional 32-bit multiplier. The report throws light on the basic principles and methods of binary multiplication process and also the power consumption issues related to multipliers. The new algorithm, which reduces the last negative signal in the partial product row is discussed to develop the new architecture. A power performance comparison is shown. The simulation results show that the new architecture is 46 % energy-efficient than a conventional multiplier at the same performance level. The number of transistors used is 34% less and also it consumes 25% less chip area in 90nm CMOS technology.

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation

Die Sarabande ist ein Tanz, der sich durch den Stilisierungsprozess im Verlauf des 17. Jahrhunderts besonders stark gewandelt hat. Der Beitrag möchte zeigen, dass Johann Jakob Froberger, Siegbert Rampe zufolge der wichtigste deutsche Komponist für Tastenmusik des 17. Jahrhunderts, an diesem Wandel wesentlich beteiligt war. Ausgehend vom frühen Sarabandentypus, wie er etwa bei Andreas Hammerschmidt und Johann Rosenmüller anzutreffen ist, wird eine Entwicklung in Frobergers Schaffen aufgezeigt, die eine fortschreitende Stilisierung erkennbar werden lässt. Das Hauptaugenmerk der Analyse liegt auf den gattungsbedingten metrischen Ambiguitäten, mittels derer Froberger einen Sarabandentypus von äußerst artifizieller Faktur und einen gleichsam spirituellen Ausdrucksgehalt hervorbringt. / The sarabande is a dance that changed significantly during the seventeenth century due to a process of stylization. This article demonstrates that Johann Jakob Froberger, according to Siegbert Rampe the most important German composer of keyboard music in the seventeenth century, played an important role in the process of this change. Starting from the early sarabande type as found in works by Andreas Hammerschmidt and Johann Rosenmüller, a development in Froberger’s work is outlined that shows a progressive stylization. The main focus of the analysis lies on genre-specific metrical ambiguities that allow Froberger to create a sarabande type of highly artificial structure and an almost spiritual expressiveness.