The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex. Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply. / The conventional approach for testing RF circuits is specification-based testing, which involves verifying sequentially all specification requirements that are promised in the data sheet. This approach is a long-time effective testapproach but nowadays suffers from significant drawbacks.First, it requires generation and capture of test signals at the DUT operating frequency. As the operational frequencies of DUT are increasing, it becomes difficult to manage signal generation and capture using ATE. As a consequence, there is a need of expensive and specialized equipment. In addition,as conventional tests target several parameters, there is a need of several data captures and multiple test configurations. As a consequence, by adding settling time between each test and test application time, the whole test time becomes very long, and the test board very complex.Another challenge regarding RF circuit testing is wafer-level testing. Indeed, the implementation of specification-based tests at wafer level is extremely difficult due to probing issues and high parasitic effects on the test interface.Moreover, multi-site testing is usually not an option due to the small count of available RF test resources, which decreases test throughput. Hence, the current practice is often to verify the device specifications only after packaging.The problem with this solution is that defective dies are identified late in the manufacturing flow, which leads to packaging loss and decreases the global yield of the process.In order to reduce production costs, there is therefore a need to develop test solutions applicable at wafer level, so that faulty circuits can be removed very early in the production flow. This is particularly important for dies designed to be integrated in Systems-In-Package (SIP).In this context, a promising solution is to develop indirect test methods. Basically, it consists in using DUT signatures to non-conventional stimuli to predict the result of conventional tests. The underlying idea is to learn during an initial phase the unknown dependency between simple measurements and conventional tests. This dependency can then be modeled through regression functions. During the testing phase, only the indirect measurements are performed and specifications are predicted using the regression model built in the learning phase.Our work has been focused on two main directions. First, we have explored the implementation of the alternate test method based on DC measurements for RF circuits and we have proposed a methodology to select the most appropriateset of DC parameters. Results from two test vehicles (a LNA using electrical simulations and a PA using real production data) indicate that the proposed methodology allows precise estimation of the DUT performances while minimizing the number of DC measurements to be carried out.Second, we have proposed a novel implementation of the alternate test strategy in order to improve confidence in alternate test predictions and to overcome the effect of limited training set sizes. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions; these devices are then are removed from the alternate test tierand directed to a second tier where further testing may apply.

Ces travaux de thèse portent sur l’étude des solutions innovantes de caractérisation destinées à l’amélioration de la précision du schéma équivalent petit signal à des fréquences d’ordre millimétrique. Après un état de l’art dans ce domaine et suite à plusieurs caractérisations au niveau composant, une nouvelle structure de test “nouvelle approche” est conçue, réalisée et caractérisée. Cette approche est basée sur une nouvelle méthode d’extraction du schéma équivalent petit signal à partir d’une structure adaptée. Cette méthode réalise une adaptation des impédances du transistor sous test aux impédances des équipements de mesure. Comme résultats, la transmission du signal entre la source et le composant sous test ainsi que la précision de la mesure des paramètres extraits sont améliorés. La méthode développée permet la validation des modèles compacts des composants fabriqués en technologie BiCMOS 0.25μm au niveau circuit. Les mesures réalisées ont montré une bonne amélioration de l’extraction entre un transistor sous test seul et un transistor sous test adapté. La méthode d’investigation proposée permet l’extraction des modèles à des très hautes fréquences avec une meilleure précision. Cette thèse ouvre donc des perspectives pour la caractérisation en bande millimétrique notamment caractérisation des structures adaptées en impédances et de méthodes de de-embedding dédiées à ces dernières. / This thesis deals with the study of innovative solutions for small signal characterization at millimeter wave frequency. After a state of the art in this field and following to several characterizations at device level, a new test structure “new approach” is designed, fabricated, and characterized. The approach of characterizing at circuit level is based on a new method to extract the small signal equivalent circuit using matched test structures. This method proposed here makes the DUT impedances carefully match the characteristic impedances of the measurement equipment. In results, the transmission of the signal from the source to the DUT is improved while the parameters extraction accuracy is improved. The developed method enables the BiCMOS 0.25μm compact models validation in circuit level in mm-Wave band and enables accurate parameter extraction in a narrow band at higher frequencies. The verification results demonstrated that the new test structure significantly outperformed the conventional method in measurement accuracy specifically in very high frequency. Some aspects of the matched test structure could be subject of further investigation. In particularly topics such as, characterization over multiple test structure geometries and deembedding test structure losses.