Bibliography: p. 76-77. / Title page reads: Final report ESL-FR-361. / NASA Research Grant NSG-496. M.I.T. Project DSR 76152.

Thesis (M.S.)--Mississippi State University. Department of Computer Science. / Title from title screen. Includes bibliographical references.

Emerging I/O density and bandwidth requirements are driving packages to low-CTE silicon, glass and organic substrates for higher wiring density and reliability of interconnections and Cu-low k dielectrics. These are needed for high performance applications as 2.5D packages in large-size, and also as ultra-thin packages for consumer applications that are directly assembled on the board without the need for an intermediate package. The trend to low-CTE packages (CTE of 3-8ppm/°C), however, creates large CTE mismatch with the board on which they are assembled. Interconnection reliability is, therefore, a major concern when low CTE interposers are surface mounted onto organic system boards via solder joints. This reliability concern is further aggravated with large package sizes and finer pitch. For wide acceptance of low CTE packages in high volume production, it is also critical to assemble them on board using standard Surface Mount Technologies (SMT) without the need for under-fill. This research aims to demonstrate reliable 400 micron pitch solder interconnections from low CTE glass interposers directly assembled onto organic boards by overcoming the above challenges using two approaches; 1) Stress-relief dielectric build up layers on the back of the interposer, 2) Polymer collar around the solder bumps for shear stress re-distribution. A comprehensive methodology based on modeling, design, test vehicle fabrication and characterization is employed to study and demonstrate the efficacy of these approaches in meeting the interposer-to-board interconnection requirements. The effect of varying geometrical and material properties of both build-up layers and polymer collar is studied through Finite Element Modeling. Interposers were designed and fabricated with the proposed approaches to demonstrate process feasibility.

Thesis (Ph. D.)--University of Washington, 2007. / Vita. Includes bibliographical references (p. 127-131).

Thesis (M.B.A.)--University of Hong Kong, 1991.

Thesis (Ph. D.)--University of Oregon, 2000. / Title from title page. Extent of document: xiii, 207 p. : ill. Includes vita and abstract. Includes bibliographical references (p. 197-207).

Thesis (M.S. in Computer Science)--Naval Postgraduate School, Dec. 2004. / Thesis Advisor(s): Wen, Su ; Gibson, John. "December 2004." Includes bibliographical references (p. 63-64). Also available in print.

Thesis (Ph. D.)--University of Cambridge, 1996. / Cover title. "October 1996." Includes bibliographical references.

Thesis (M.E.E.)--University of Delaware, 2005. / Principal faculty advisor: Kenneth Barner, Dept. of Electrical and Computer Engineering. Includes bibliographical references.

Thesis (M. Sc.)--University of Canterbury, 2006. / Typescript (photocopy). Includes bibliographical references (leaves 83-89). Also available via the World Wide Web.