nÃo hà / O presente trabalho propÃe o estudo do conversor boost CC-CC de alto ganho de tensÃo baseado na cÃlula de comutaÃÃo de trÃs estados e nas cÃlulas multiplicadoras de tensÃo (mc). Este trabalho investiga um modelo matemÃtico para o citado conversor. A anÃlise proposta à baseada na ferramenta âmodelagem do interruptor PWM para conversores CC-CCâ. O modelo deve ser encontrado por uma simples inspeÃÃo do circuito do conversor. Deve ser possÃvel aplicÃ-lo para realizar diversas anÃlises, como em regime permanente, regime transitÃria e anÃlise de pequenos sinais por meio de um uma abordagem unificada. Considerando um dado nÃmero de cÃlulas multiplicadoras de tensÃo, duas situaÃÃes sÃo analisadas com esta ferramenta: operaÃÃo com uma Ãnica cÃlula multiplicadora de tensÃo (mc=1) e vÃrias cÃlulas multiplicadoras de tensÃo (mc> 1). O mÃtodo proposto à validado por simulaÃÃes e à verificada sua efetividade. AlÃm disso, à analisado neste trabalho o controle modo corrente mÃdia convencional, o qual à aplicado em uma das configuraÃÃes em estudo. O rendimento do conversor e a efetividade do controlador proposto sÃo demonstrados por resultados experimentais para um protÃtipo do laboratÃrio de 1 kW. / The present work proposes the study of the boost converter based on three-state switching cell and voltage multipliers cells (mc). A mathematical model of the aforementioned converter is investigated here. The proposed analysis is based on the tool named âPWM-Switch Modeling of DC-DC Convertersâ. The model must be found by a simple inspection of the converterâs circuit. It is possible to apply such model in order to realize various analyses such as steady-state, transient, and small-signal analysis in a single and same model. Considering the number of voltage multipliers cells (mc), two situations are analyzed: operation with a single multiplier cell (mc=1) and operation with multiple voltage multiplier cells (mc>1).The proposed method was validated through simulations and its effectiveness was verified. In addition to this, conventional average current mode control is also applied to one of the studied configurations. The performance of the converter and the effectiveness of the proposed controller are demonstrated by experimental results obtained from a 1-kW laboratory prototype.

No description available.

The diploma thesis is describing how forward converter works. The diploma thesis presents the function of forward converter with demagnetizing winding and presents the function of two-switched forward converter. The diploma thesis descibes the behaviour of continuous current mode and discontinuous current mode. The diploma thesis explains the reasons for implementation feedback and presents the basic types of compensations. The project deals with AC analysis of two-switched forward converter with continuous peak current mode control. The Analog prototyping metod is used for digital control design. The function of the converter was tested in laboratory. The laboratory results have been compared with the theoretical and the simulation results.

La sophistication grandissante des dispositifs intelligents ultra-portatifs, tels que les smartphones ou les tablettes,crée un besoin d'amélioration des performances des organes de conversion de puissance.La tendance des technologies d'acheminement de puissance évolue progressivement vers une fréquence plus élevée, une meilleure densité d'intégration et une plus grande flexibilité dans les schémas d'asservissement. La modulation dynamique de tension est utilisée dans les circuits intégrés de gestion de puissances(DVS PMICs)des transmetteurs RF alors que la modulation DVFS est utilisée dans les PMICs dédiées au CPUs et GPUs. Des DCDC flexibles et fonctionnant à haute fréquence constituent aujourd'hui la solution principale en conjonction avec des régulateurs à faible marge de tension (LDO).L'évolution vers des solutions à base de HFDCDC de faibles dimensions pose un défi sérieux en matière de 1)stabilité des boucles d'asservissement,2)de complexité des architectures de contrôle imbriquant des machines d'état asynchrones pour gérer une large dynamique de puissance de sortie et 3)de portabilité de la solutions d'une technologie à une autre.Les solutions les plus courantes atteignent aujourd'hui une gamme de 2 à 6 Mhz de fréquence de découpage grâce à l'usage de contrôleurs à hystérésis qui souffrent de la difficulté à contenir la fréquence de découpage lors des variations de la tension ou du courant en charge.Nous avons voulu dans ce travail étendre l'usage des méthodes de conception et de modélisation conventionnelles comme le modèle petit signal moyen, dans une perspective de simplification et de création de modèles paramétriques. L'objectif étant de rendre la technique de compensation flexible et robuste aux variations de procédés de fabrication ou bien aux signaux parasités inhérents à la commutation de puissance.Certes, le modèle moyen petit signal, au demeurant bien traité dans la littérature, réponds amplement à la problématique de compensation des DCDCs notamment quand la stabilité s'appuie sur le zéro naturel à haute fréquence inhérent à la résistance série ESR de la capacité de sortie, mais les HFDCDC actuels utilisent des capacités MLCC ayant une très faible ESR et font appel à des techniques de compensation paramétriques imbriquant le schéma de compensation dans la génération même du rapport cyclique. La littérature existante sur le fonctionnement de la machine d'état, se contente d'une description simpliste de convertisseurs PWM/PFM mais ne donne que très peu d'éléments sur la gestion des opérations synchrones/asynchrones alternant PWM,PFM,écrêtage de courant, démarrage ou détection de défaillance. Dans ce travail, notre études est axée sur les deux aspects suivants:1)La modélisation paramétrique et la compensation de la boucle d'asservissement de HFDCDC et 2)la portabilité de la conception de la machine d'états du contrôleur notamment lorsqu'elle intègre des transitions complexes entre les modes.Dans la première section, nous avons développé un modèle petit signal moyen d'un convertisseur Buck asservi en mode courant-tension et nous l'avons analysé pour faire apparaitre les contributions proportionnelle, intégrale et dérivé dans la boucle. Nous avons démontré la possibilité d'utiliser le retour en courant pour assurer l'amortissement nécessaire et la stabilité de la boucle pour une large dynamique de variations des conditions de charge.Dans la seconde section, nous avons développé une architecture de machine d'états sophistiquée basé sur la méthode d'Huffman avec un effort substantiel d'abstraction que nous a permis de la concevoir en description RTL pour une gestion fiable du fonctionnement asynchrone et temps réel.Notre contribution théorique a fait l'objet d'une réalisation d'un PMIC de test comportant deux convertisseurs Buck cadencés à 12MHz en technologie BiCMOS 0.5um/0.18um. Les performances clefs obtenues sont:une surtension de 50mV pendant 2us suite à l'application d'un échelon de courant de 300mA. / The continuous sophistication of smart handheld devices such as smartphones and tablets creates an incremental need for improving the performances of the power conversion devices. The trend in power delivery migrates progressively to higher frequency, higher density of integration and flexibility of the control scheme. Dynamic Voltage Scaling Power Management ICs (DVS PMIC) are now systematically used for powering RF Transmitters and DVFS PMICS using Voltage and Frequency scaling are used for CPUs and GPUs. Flexible High frequency (HF) DC/DC converters in conjunction with low dropout LDOs constitute the main solution largely employed for such purposes. The migration toward high frequency/small size DCDC solutions creates serious challenges which are: 1) the stability of the feedback loop across a wide range of loading voltage and current conditions 2) The complexity of the control and often-non-synchronous state machine managing ultra large dynamics and bridging low power and high power operating modes, 3) The portability of the proposed solution across technology processes.The main stream solutions have so far reached the range of 2 to 6 MHz operation by employing systematically sliding mode or hysteretic converters that suffer from their variable operating frequency which creates EMI interferences and lead to integration problems relative to on-chip cross-talk between converters.In this work we aim at extend the use of traditional design and modeling techniques of power converters especially the average modeling technique by putting a particular care on the simplification of the theory and adjunction of flexible compensation techniques that don't require external components and that are less sensitive to process spread, or to high frequency substrate and supply noise conditions.The Small Signal Average Models, widely treated in the existing literature, might address most needs for system modeling and external compensation snubber design, especially when aiming on the high frequency natural zero of the output capacitor. However, HFDCDC converters today use small size MLCC capacitors with a very low ESR which require using alternative techniques mixing the compensation scheme with the duty cycle generation itself. The literature often provides a simplistic state machine description such as PWM/PFM operations but doesn't cover combined architectures of synchronous / non synchronous mode operations such as PWM, PFM, Current Limit, Boundary Clamp, Start, Transitional and finally Fault or Protection modes.In our work, we have focused our study on two main axes: 1) The parametric modeling and the loop compensation of HFDCDC and 2) the scalability of the control state machine and mode inter-operation. In the first part, we provided a detailed small signal averaged model of the “voltage and current mode buck converter” and we depicted it to emphasize and optimize the contributions of the Proportional, Integral and Derivative feedback loops. We demonstrated the ability to use the current feedback to damp and stabilize the converter with a wide variety of loading conditions (resistive or capacitive). In the second part, we provided architecture of the mode control state machine with different modes like the PWM, PFM, soft-start, current limit,… .The technique we have used is inspired by Huffman machine with a significant effort to make it abstract and scalable. The state machine is implemented using RTL coding based on a generic and scalable approach.The theoretical effort has been implemented inside a real PMIC test-chip carrying two 12MHz buck converters, each employing a voltage and current mode feedback loop. The chip has been realized in a 0.5um / 0.18um BiCMOS technology and tested through a dedicate Silicon validation platform able to test the analog, digital and power sections. The key performance obtained is a 50mV load transient undershoot / overshoot during 2us following a load step of 300mA (slope 0.3A/ns).

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-24T19:07:44Z No. of bitstreams: 1 pedromachadodealmeida.pdf: 10367147 bytes, checksum: 04b7cf913c75cb9f82395bf7b9769825 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-25T15:25:19Z (GMT) No. of bitstreams: 1 pedromachadodealmeida.pdf: 10367147 bytes, checksum: 04b7cf913c75cb9f82395bf7b9769825 (MD5) / Made available in DSpace on 2017-04-25T15:25:19Z (GMT). No. of bitstreams: 1 pedromachadodealmeida.pdf: 10367147 bytes, checksum: 04b7cf913c75cb9f82395bf7b9769825 (MD5) Previous issue date: 2013-11-29 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / A presente tese contribui para a análise, modelagem e projeto de controladores discretos de um sistema de geração fotovoltaico de 30 kWp conectado à rede elétrica sem filtros passivos. O conversor fonte de tensão (VSC) de interface é interligado a rede elétrica usando somente as indutâncias de dispersão de um banco de transformadores monofásicos como filtros harmônicos. Modelos discretos são desenvolvidos tanto para o lado CC quanto para o lado CA do conversor. A modelagem do lado CA foi feita nos sistemas de coordenadas αβ0 e dq0. Já a modelagem da dinâmica do lado CC foi feita no sistema de coordenadas dq de acordo com balanço de potência entre os terminais do VSC. Baseado nos modelos obtidos, duas estratégias básicas foram investigadas e discutidas para projetar os compensadores discretos usados para controlar as correntes sintetizadas por um sistema de geração fotovoltaico no modo de corrente. Resultados experimentais mostram que o uso apenas de controladores lineares, proporcional–integral (PI) e proporcional–ressonante (PR), sintonizados na componente fundamental não é suficiente para manter a qualidade das correntes geradas dentro dos padrões internacionais, devido a operação não linear do transformador de conexão. Para contornar o problema anterior duas soluções foram investigadas: (i) inclusão de múltiplos controladores ressonantes nas coordenadas αβ; e (ii) inclusão de um controlador repetitivo em paralelo com o controlador PI nas coordenadas dq. Resultados experimentais mostraram que ambas estratégias são adequadas para compensar as componentes harmônicas. Finalmente, foi proposta uma estratégia para controlar o conversor durante faltas assimétricas (Fault–ride through) e eliminar as oscilações no barramento CC durante condições de desbalanço. O controlador proposto é composto por uma parcela PI e duas parcelas ressonantes, as quais controlam as componentes média e oscilante, através da injeção correntes de sequencia positiva e negativa na rede, respectivamente. Resultados de simulação mostram que o controlador proposto é adequado para eliminar as oscilações no barramento CC sem prejudicar as estabilidade do sistema. / The current thesis contributes to the analysis, modelling and design of discrete time controllers which aim is to control a 30 kWp photovoltaic dispersed generation system connected to the electric grid without passive filters. In fact, the interface voltage– sourced converter (VSC) is connected to the grid using only the leakage inductance of a single–phase transformer bank as harmonic filters. Initially, discrete time models are developed to the converter’s DC–side as well as to the AC–side. The AC–side modelling is performed on αβ0 and dq0 coordinate systems. On the other hand, the DC–side dynamics are modeled on the dq frame according to the power balance between the converter’s terminals. Based on the models obtained, strategies to control the converter in the current mode control on the αβ and dq are developed and a methodology to design the controllers are addressed in details. Experimental results shown that only the use of linear controllers, proportional–integral (PI) and proportional–resonant (PR), tuned on the fundamental component are not sufficient to guarantee the quality of the generated currents according to international standards. This is due to the operation of the connection transformer in a nonlinear region. In order to overcome this drawback, two solutions are taken into account: (i) inclusion of several parallel resonant controller in αβ frame; and (ii) inclusion of a repetitive controller in parallel with the PI controller in the dq frame. Experimental results shown that both strategies are suitable to compensate the harmonic components on the output current. Finally, a strategy is proposed to control the system under asymmetrical faults (fault–ride through) and to mitigate the voltage oscillation on the DC–side during unbalance conditions. The proposed controller is composed of a PI part and two resonant parts, which controls the average and the oscillating voltage components, through the injection of positive and negative sequence currents into the grid, respectively. Simulation results shown that the proposed controller is suitable to mitigate the DC–side voltage oscillations without jeopardizing the system stability.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-26T12:14:24Z No. of bitstreams: 1 gabrielazevedofogli.pdf: 13619054 bytes, checksum: d260cb2571f242e43eab89132a03d62c (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-26T12:26:45Z (GMT) No. of bitstreams: 1 gabrielazevedofogli.pdf: 13619054 bytes, checksum: d260cb2571f242e43eab89132a03d62c (MD5) / Made available in DSpace on 2017-04-26T12:26:45Z (GMT). No. of bitstreams: 1 gabrielazevedofogli.pdf: 13619054 bytes, checksum: d260cb2571f242e43eab89132a03d62c (MD5) Previous issue date: 2014-03-19 / CAPES - Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / Esta dissertação apresenta um estudo de conexão de um grupo gerador-diesel (GMG) trifásico em uma rede secundária de distribuição de energia elétrica. A integração do GMG é feita por uma unidade de processamento de energia (PPU) composta por um retificador trifásico não controlado conectado em série com um conversor fonte de tensão (VSC) modulado com uma estratégia de modulação por largura de pulso. O GMG pode operar de duas maneiras distintas: (i) modo standby (interligado) ou (ii) modo isolado. O conversor de saída da PPU pode ser controlado para injetar potência ativa na rede CA, ou como um filtro ativo de potência (FAP) compensando potência reativa e correntes harmônicas nos terminais das cargas. O VSC de interface é controlado no modo de corrente (CMC), sendo seus controladores projetados a partir de funções de transferência obtidas com o modelo matemático do sistema elétrico nas coordenadas dq0. Esses controladores são projetados com múltiplos integradores para garantir a qualidade da forma de onda da corrente injetada na rede CA. Dependendo do modo de operação é utilizada uma malha adicional para regular a tensão do barramento CC do conversor de interface. Para validar o modelo matemático e o algoritmo de controle são realizadas simulações digitais no programa PSIM. Resultados experimentais, obtidos com um protótipo de laboratório, cujos controladores foram implementados em um processador digital de sinais TMS320F28335 da Texas Instruments, são usados para validar as estratégias de controle propostas. / This dissertation presents a study about the connection of a three-phase Diesel Genset (DG) to a secondary distribution network. The integration of DG is done by a Power Processing Unit (PPU) composed of a three-phase rectifier connected in series with a Pulse Width Modulated Voltage Source Converter (VSC). The DG can operate in two distinct modes: (i) standby (interconnected) or (ii) islanding. The PPU’s output converter can be controlled to inject active power into AC electric grid, or as an Active Power Filter (APF), compensating the reactive power and harmonics currents at the load terminals. The VSC is controlled employing the current mode control (CMC), and its compensators are designed based on the electrical system transfer function in dq0 coordinates. Multiple rotating synchronous reference frame integrators (PI-MRI) are used to ensure the quality of the generated power. Depending on the operating mode, an additional loop is used to regulate the DC bus voltage. In order to validate the mathematical model and the control algorithm, digital simulations using PSIM are performed. Experimental results obtained with the prototype, which controllers were implemented in a TMS320F28335 of Texas Instruments are used to validate the proposed control strategies.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

Submitted by Renata Lopes (renatasil82@gmail.com) on 2017-04-20T13:39:03Z No. of bitstreams: 1 pedromachadodealmeida.pdf: 13436160 bytes, checksum: 84c66613dade0766ae9ea2bdc8be9f91 (MD5) / Approved for entry into archive by Adriana Oliveira (adriana.oliveira@ufjf.edu.br) on 2017-04-20T14:45:37Z (GMT) No. of bitstreams: 1 pedromachadodealmeida.pdf: 13436160 bytes, checksum: 84c66613dade0766ae9ea2bdc8be9f91 (MD5) / Made available in DSpace on 2017-04-20T14:45:37Z (GMT). No. of bitstreams: 1 pedromachadodealmeida.pdf: 13436160 bytes, checksum: 84c66613dade0766ae9ea2bdc8be9f91 (MD5) Previous issue date: 2011-04-29 / Esta dissertação apresenta uma estratégia de controle para sistemas de geração fotovoltaicos, de único estágio, trifásicos, conectados à rede elétrica de distribuição. São desenvolvidos modelos matemáticos para representar as características dinâmicas dos painéis fotovoltaicos, do conversor fonte de tensão (VSC -“Voltage Source Converter”) e da rede de distribuição. A modelagem do sistema de geração disperso (SGD) é feita no sistema de coordenadas síncrono (dq), fornecendo um sistema de equações diferenciais que pode ser usado para descrever o comportamento dinâmico do sistema quando as tensões da rede estão equilibradas ou desequilibradas. O conversor é controlado no modo de corrente, através da estratégia de modulação vetorial (Space Vector Modulation - SVM). São projetadas duas malhas de controle em cascata para controlar o conversor estático. A malha interna controla a corrente injetada na rede enquanto que a externa controla a tensão no barramento CC do conversor. O controle da tensão CC permite rastrear o ponto de máxima potência do painel PV além de controlar a quantidade de potência ativa injetada na rede CA. Um método ativo de detecção de ilhamento baseado na injeção de corrente de sequência negativa é incorporado ao sistema de controle. Resultados de simulações digitais obtidos com o programa ATP (Alternative Transient Program ) são utilizados para validar os modelos matemáticos e as estratégias de controle. Finalmente, um protótipo experimental de pequena escala é montado em laboratório. Todo o sistema de controle do protótipo experimental foi implementado no DSP TMS320F28212. Os resultados obtidos demonstram o funcionamento do sistema e podem ser usados para validar a estratégia de controle utilizada. / This dissertation presents a control strategy for a single-stage, three-phase, photovoltaic systems to be connected to a distribution network. Mathematical models are developed to represent the dynamic characteristics of the photovoltaic panels, the voltage-source converter (VSC) and the distribution network. The modeling of the dispersed generation system (DGS) is done in the synchronous reference frame (dq), providing a system of differential equations that describes the dynamic behavior of the system when the network voltages are balanced or unbalanced. The converter is controlled in current mode through the space vector modulation (SVM) strategy. Two control loops are designed to control the static converter. The inner loop controls the injected current into the network while the external loop controls the converter DC bus voltage. The DC voltage regulator allows to track the PV maximum power point and to control the active power injected into the AC grid. An active islanding detection method based on negative-sequence current injection is incorporated into the control system. Digital simulations results obtained with Alternative Transients Program (ATP) is used to validate the mathematical models and the control strategies. Finally, a small-scale experimental prototype is implemented in the laboratory. The whole control system of the experimental prototype was programmed in DSP TMS320F2812 of Texas Instruments. The results demonstrate that the operation of the system can be used to validate the applied control strategy.