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A Synthesizable VHDL Model of the Serial Communication Interface and Synchronous Serial Interface of Motorola DSP56002Mattam, Swaroop January 2006 (has links)
<p>The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. The SCI block is able to handle a data rate of 5Mbps in Synchronous mode and 625Kbps in asynchronous mode for a 40MHz clock. It supports five word formats including a multidrop mode for multiprocessor systems. SSI provides a data rate of 10Mbps for the same 40 MHz clock. The design includes a programmable on-chip or external baud rate generator/interrupt timer for the SCI and a clock generator and frame Sync generator for the SSI.</p><p>The thesis focus on arriving at a full functional description of individual blocks included with Port C from the data sheets and product users manual. From this operational description a behavioural model was developed. The structure and implementation is based on the Motorola DSP56002 with additional support for a variable data-width. The model is written completely in behavioural VHDL with a top-down approach and the model was verified and validated.</p>
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A Synthesizable VHDL Model of the Serial Communication Interface and Synchronous Serial Interface of Motorola DSP56002Mattam, Swaroop January 2006 (has links)
The design and implementation of a synthesizable model of the Serial Communication Interface and Synchronous Serial Interface, which constitutes the Port C of Motorola DSP56002 is presented in this report. They serves as a full duplex serial interface to other DSPs, processors, codecs, digital-to-analog and analog-to-digital converters and other transducers. The SCI block is able to handle a data rate of 5Mbps in Synchronous mode and 625Kbps in asynchronous mode for a 40MHz clock. It supports five word formats including a multidrop mode for multiprocessor systems. SSI provides a data rate of 10Mbps for the same 40 MHz clock. The design includes a programmable on-chip or external baud rate generator/interrupt timer for the SCI and a clock generator and frame Sync generator for the SSI. The thesis focus on arriving at a full functional description of individual blocks included with Port C from the data sheets and product users manual. From this operational description a behavioural model was developed. The structure and implementation is based on the Motorola DSP56002 with additional support for a variable data-width. The model is written completely in behavioural VHDL with a top-down approach and the model was verified and validated.
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Ogg Vorbis decoder for Motorola DSP56002 / Ogg Vorbis avkodare för Motorola DSP56002Barsk, Niklas January 2004 (has links)
<p>Ogg Vorbis is a rather new audio format with some similarities with other more known formats such as MP3 and WMA. It is generally accepted to have a better audio quality than most competing formats and it is in contrast to many of its competitors totally licence and royalty free. </p><p>The goal with this thesis is to port the existing fixed point decoder Tremor, which is written in C, to Motorola's DSP56002. The DSP has a very limited amount of memory so some optimizations has to be made to be able to run Tremor successfully. </p><p>The report presents the necessary steps taken to port Tremor to the DSP and the difficulties of this process. It also describes the memory and CPU usage of the DSP when running Tremor and other results of the port. </p><p>A description as well as examples and workarounds of bugs found in the compiler g56k is attached to this report.</p>
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Ogg Vorbis decoder for Motorola DSP56002 / Ogg Vorbis avkodare för Motorola DSP56002Barsk, Niklas January 2004 (has links)
Ogg Vorbis is a rather new audio format with some similarities with other more known formats such as MP3 and WMA. It is generally accepted to have a better audio quality than most competing formats and it is in contrast to many of its competitors totally licence and royalty free. The goal with this thesis is to port the existing fixed point decoder Tremor, which is written in C, to Motorola's DSP56002. The DSP has a very limited amount of memory so some optimizations has to be made to be able to run Tremor successfully. The report presents the necessary steps taken to port Tremor to the DSP and the difficulties of this process. It also describes the memory and CPU usage of the DSP when running Tremor and other results of the port. A description as well as examples and workarounds of bugs found in the compiler g56k is attached to this report.
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