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The recently developed gate turn-off thyristor is now becoming well established as the first choice switching device in high power converters for applications such as uninterruptible power supplies, frequency changers, and AC and some DC variable speed motor drives. The special operating features of these devices in conventional circuit configurations are investigated. The GTO thyristor physical behaviour and operating characteristics are first described and supported by measurements made at turn-off currents of up to 600A on a specially constructed test circuit. From this, it is shown that, owing to the extremely fast rates of fall of anode current at turn-off, voltage overshoot effects caused by the stray circuit inductances are highly dangerous to the device, and effective snubbing is essential. A detailed study of these stray inductance effects in constructed DC chopper and H-bridge inverter circuits follows. The circuits are modelled to include these strays, with appropriate mathematical analysis and computer simulation, to determine which stray inductances are the most influential in causing GTO thyristor voltage stress. The different switching patterns are considered for the H-bridge to provide quasi-square and various pulse width modulated (PWM) output voltage waveforms, and the detailed current transfer paths in the various circuit devices and snubber components defined and mathematically analysed in each case. Practical switching effects of diode reverse recovery and GTO mismatched switching times are demonstrated and possible damaging conditions revealed. All analytical and computed results are supported by experimental measurements. A GTO thyristor will be damaged by attempting to turn-off an over-current, and satisfactory protection against this is essential. Conventional fusing is usually inadequate, and a better method is to use a fast active system utilising either a crowbar and fuse, or rapid direct gate turn-off. Both methods are investigated and experimental results provided. It is concluded that, with appropriate circuit layout and component choice, the unavoidable stray inductance effects can be limited to manageable levels. The most severe effects are caused by the DC source inductance which is the most difficult to minimise. Others within the power circuit, if kept small, will have a marginal effect. Fast over-current protection is achievable