abstract: Microelectronic industry is continuously moving in a trend requiring smaller and smaller devices and reduced form factors with time, resulting in new challenges. Reduction in device and interconnect solder bump sizes has led to increased current density in these small solders. Higher level of electromigration occurring due to increased current density is of great concern affecting the reliability of the entire microelectronics systems. This paper reviews electromigration in Pb- free solders, focusing specifically on Sn0.7wt.% Cu solder joints. Effect of texture, grain orientation, and grain-boundary misorientation angle on electromigration and intermetallic compound (IMC) formation is studied through EBSD analysis performed on actual C4 bumps. / Dissertation/Thesis / M.S. English 2013

abstract: Electromigration in metal interconnects is the most pernicious failure mechanism in semiconductor integrated circuits (ICs). Early electromigration investigations were primarily focused on aluminum interconnects for silicon-based ICs. An alternative metallization compatible with gallium arsenide (GaAs) was required in the development of high-powered radio frequency (RF) compound semiconductor devices operating at higher current densities and elevated temperatures. Gold-based metallization was implemented on GaAs devices because it uniquely forms a very low resistance ohmic contact and gold interconnects have superior electrical and thermal conductivity properties. Gold (Au) was also believed to have improved resistance to electromigration due to its higher melting temperature, yet electromigration reliability data on passivated Au interconnects is scarce and inadequate in the literature. Therefore, the objective of this research was to characterize the electromigration lifetimes of passivated Au interconnects under precisely controlled stress conditions with statistically relevant quantities to obtain accurate model parameters essential for extrapolation to normal operational conditions. This research objective was accomplished through measurement of electromigration lifetimes of large quantities of passivated electroplated Au interconnects utilizing high-resolution in-situ resistance monitoring equipment. Application of moderate accelerated stress conditions with a current density limited to 2 MA/cm2 and oven temperatures in the range of 300°C to 375°C avoided electrical overstress and severe Joule-heated temperature gradients. Temperature coefficients of resistance (TCRs) were measured to determine accurate Joule-heated Au interconnect film temperatures. A failure criterion of 50% resistance degradation was selected to prevent thermal runaway and catastrophic metal ruptures that are problematic of open circuit failure tests. Test structure design was optimized to reduce resistance variation and facilitate failure analysis. Characterization of the Au microstructure yielded a median grain size of 0.91 ìm. All Au lifetime distributions followed log-normal distributions and Black's model was found to be applicable. An activation energy of 0.80 ± 0.05 eV was measured from constant current electromigration tests at multiple temperatures. A current density exponent of 1.91 was extracted from multiple current densities at a constant temperature. Electromigration-induced void morphology along with these model parameters indicated grain boundary diffusion is dominant and the void nucleation mechanism controlled the failure time. / Dissertation/Thesis / Ph.D. Materials Science and Engineering 2013

A Eletromigração (EM) nas interconexões de metal em um chip é um mecanismo crítico de falhas de confiabilidade em tecnologias de escala nanométrica. Os trabalhos na literatura que abordam os efeitos da EM geralmente estão preocupados com estes efeitos nas redes de distribuição de potência e nas interconexões entre as células. Este trabalho aborda o problema da EM em outro aspecto, no interior das células, e aborda especificamente o problema da eletromigração em interconexões de saída, Vdd e Vss dentro de uma célula padrão onde há poucos estudos na literatura que endereçam esse problema. Até onde sabe-se, há apenas dois trabalhos na literatura que falam sobre a EM no interior das células. (DOMAE; UEDA, 2001) encontrou buracos formados pela EM nas interconexões de um inversor CMOS e então propôs algumas ideias para reduzir a corrente nos segmentos de fio onde formaram-se buracos. O outro trabalho, (JAIN; JAIN, 2012), apenas cita que a EM no interior das células padrão deve ser verificada e a frequência segura das células em diferentes pontos de operação deve ser modelada. Nenhum trabalho da literatura analisou e/ou modelou os efeitos da EM nos sinais dentro das células. Desta forma, este é o primeiro trabalho a usar o posicionamento dos pinos para reduzir os efeitos da EM dentro das células. Nós modelamos a eletromigração no interior das células incorporando os efeitos de Joule heating e a divergência da corrente e este modelo é usado para analisar o tempo de vida de grandes circuitos integrados. Um algoritmo eficiente baseado em grafos é desenvolvido para acelerar a caracterização da EM no interior das células através do cálculos dos valores de corrente média e RMS. Os valores de corrente computados por esse algoritmo produzem um erro médio de 0.53% quando comparado com os valores dados por simulações SPICE. Um método para otimizar a posição dos pinos de saída, Vdd e Vss das células e consequentemente otimizar o tempo de vida do circuito usando pequenas modificações no leiaute é proposto. Para otimizar o TTF dos circuitos somente o arquivo LEF é alterado para evitar as posições de pino críticas, o leiaute da célula não é alterado. O tempo de vida do circuito pode ser melhorado em até 62.50% apenas evitando as posições de pino críticas da saída da célula, 78.54% e 89.89% evitando as posições críticas do pino de Vdd e Vss, respectivamente Quando as posições dos pinos de saída, Vdd e Vss são otimizadas juntas, o tempo de vida dos circuitos pode ser melhorado em até 80.95%. Além disso, nós também mostramos o maior e o menor tempo de vida sobre todos as posições candidatas de pinos para um conjunto de células, onde pode ser visto que o tempo de vida de uma célula pode ser melhorado em até 76 pelo posicionamento do pino de saída. Além disso, alguns exemplos são apresentados para explicar porque algumas células possuem uma melhora maior no TTF quando a posição do pino de saída é alterada. Mudanças para otimizar o leiaute das células são sugeridas para melhorar o tempo de vida das células que possuem uma melhora muito pequena no TTF através do posicionamento dos pinos. A nível de circuito, uma análise dos efeitos da EM é apresentada para as diferentes camadas de metal e para diferentes comprimentos de fios para os sinais (nets) que conectam as células. / Electromigration (EM) in on-chip metal interconnects is a critical reliability failure mechanism in nanometer-scale technologies. Usually works in the literature that address EM are concerned with power network EM and cell to cell interconnection EM. This work deals with another aspect of the EM problem, the cell-internal EM. This work specifically addresses the problem of electromigration on signal interconnects and on Vdd and Vss rails within a standard cell. Where there are few studies in the literature addressing this problem. To our best knowledge we just found two works in the literature that talk about the EM within a cell. (DOMAE; UEDA, 2001) found void formed due to electromigration in the interconnection portion in a CMOS inverter and then proposes some ideas to reduce the current through the wire segments where the voids were formed. The second work, (JAIN; JAIN, 2012), just cites that the standard-cell-internal-EM should be checked and the safe frequency of the cells at different operating points must be modeled. No previous work analyzed and/or modeled the EM effects on the signals inside the cells. In this way, our work is the first one to use the pin placement to reduce the EM effects inside of the cells. In this work, cell-internal EM is modeled incorporating Joule heating effects and current divergence and is used to analyze the lifetime of large benchmark circuits. An efficient graph-based algorithm is developed to speed up the characterization of cell-internal EM. This algorithm estimates the currents when the pin position is moved avoiding a new characterization for each pin position, producing an average error of just 0.53% compared to SPICE simulation. A method for optimizing the output, Vdd and Vss pin placement of the cells and consequently to optimize the circuit lifetime using minor layout modifications is proposed. To optimize the TTF of the circuits just the LEF file is changed avoiding the critical pin positions, the cell layout is not changed. The circuit lifetime could be improved up to 62.50% at the same area, delay, and power because changing the pin positions affects very marginally the routing. This lifetime improvement is achieved just avoiding the critical output pin positions of the cells, 78.54% avoiding the critical Vdd pin positions, 89.89% avoiding the critical Vss pin positions and up to 80.95% (from 1 year to 5.25 years) when output, Vdd, and Vss pin positions are all optimized simultaneously. We also show the largest and smallest lifetimes over all pin candidates for a set of cells, where the lifetime of a cell can be improved up to 76 by the output pin placement. Moreover, some examples are presented to explain why some cells have a larger TTF improvement when the output pin position is changed. Cell layout optimization changes are suggested to improve the lifetime of the cells that have a very small TTF improvement by pin placement. At circuit level, we present an analysis of the EM effects on different metal layers and different wire lengths for signal wires (nets) that connect cells.

Ce travail porte sur les mécanismes de densification de systèmes métalliques par frittage flash (spark plasma sintering, SPS). Dans ce procédé actuellement en plein essor, la poudre est densifiée en présence de pulses de courant électrique très intenses. La cinétique de densification étant beaucoup plus rapide que par les techniques conventionnelles, de nombreuses études dans le monde portent actuellement sur l'effet des pulses de courant. Les hypothèses habituelles font état d'arcs et de plasma entre particules de poudre, de surchauffe localisée au niveau des ponts, d'électromigration et d'électroplasticité. Dans cette étude, nous avons considéré des conducteurs électriques, TiAl et Ag-Zn, pour mettre en évidence de tels effets. Des prélèvements de lames minces de microscopie électronique en transmission (MET) par faisceau d'ions focalisé au niveau des ponts entre particules de poudre de TiAl ont montré l'absence de surchauffes dans ces zones. Par ailleurs, les mécanismes de plasticité identifiés par MET étaient classiques. Des comparaisons avec le pressage à chaud, méthode conventionnelle de frittage, ont montré que le courant n'accélérait pas ces mécanismes. Des études modèles de déformation à chaud d'échantillons massifs ont montré que, dans les conditions thermomécaniques de sollicitation des particules de poudre, la plasticité impliquait des mécanismes de maclage, de glissement et de montée des dislocations, accompagnés de restauration et de recristallisation dynamiques, et que la cinétique résultante était contrôlée par la diffusion en volume de l'Al. Enfin, des études d'électromigration dans des couples de diffusion Ag-Zn ont montré l'absence d'influence de courants, même très intenses, sur la diffusion. Ces résultats, qui montrent l'absence d'électromigration et de phénomènes spécifiques aux ponts entre particules de poudre, apportent des réponses décisives sur les mécanismes controversés de densification par SPS. / This study reports on the densification mechanisms in metallic systems by the spark plasma sintering (SPS) technique. In this emerging powder metallurgy process, the powder is densified under pressure in presence of electric current pulses of high intensity. The sintering kinetics being much faster than that of the conventional techniques, many studies aim at exploring the potentially original mechanisms involved. Thus, sparks and plasma between powder particles, local overheating phenomena, electromigration and electroplasticity mechanisms, are postulated to occur during densification by SPS. In this study, electric conductors, TiAl and Ag-Zn, have been selected to evidence such effects. Focused ion beam lift-outs of transmission electron microscopy (TEM) thin foils at the necks between TiAl powder particles showed the absence of overheating in these zones, and that the plasticity mechanisms identified were classical. Comparisons with the classical hot pressing technique showed no acceleration of these mechanisms by the current. Model studies of deformation at high temperature of bulk samples indicated that, in the thermomechanical conditions of solicitation of the powder particles, plasticity occurred by mechanisms of twinning, glide and climb of the dislocations, accompanied by dynamic recovery and recrystallization, and that the resulting kinetics was controlled by volume diffusion of Al. Finally, electromigration studies in Ag-Zn diffusion couples showed that currents, even very intense, did not have an effect on diffusion mechanism. These results, showing no electromigration and no specific phenomena at the necks between the powder particles, provide decisive answers about the controversial SPS densification mechanisms.

abstract: Miniaturization of microdevices comes at the cost of increased circuit complexity and operating current densities. At high current densities, the resulting electron wind imparts a large momentum to metal ions triggering electromigration which leads to degradation of interconnects and solder, ultimately resulting in circuit failure. Although electromigration-induced defects in electronic materials can manifest in several forms, the formation of voids is a common occurrence. This research aims at understanding the morphological evolution of voids under electromigration by formulating a diffuse interface approach that accounts for anisotropic mobility in the metallic interconnect. Based on an extensive parametric study, this study reports the conditions under which pancaking of voids or the novel void ‘swimming’ regimes are observed. Finally, inferences are drawn to formulate strategies using which the reliability of interconnects can be improved. / Dissertation/Thesis / Masters Thesis Materials Science and Engineering 2020

The theoretical part of diploma thesis „Selection of a suitable type of flux for wave soldering”, is devoted to problematic of fluxes, flux residues and wave soldering. It introduces reader with requirements of company HC electronics and with selection of a suitable types of fluxes for testing. It also contains theoretical comparison and design of flux testing methodologies. The practical part of the diploma thesis is focused on the selection of a suitable flux for the company HC electronics by performing practical tests according to the previously proposed methodologies, which include wetting balance test method, surface insulation resistance measurement, copper mirror test, soldering test of PCB and ROSE method.

The presence of inorganic ions is one of the criteria for thermal water assessing. The most important anions that affect the water quality and allow their use for therapeutic purposes, include sulfates, chlorides, nitrates and bicarbonates. Ions (as sodium, potassium, calcium and magnesium) are the significant cations. The ion chromatography is used for separation of these substances and also some methods based on electrophoretic migration of ions in an electric field. The electromigration method of isotachophoresis was chosen for determination of selected ions in water samples collected from thermal boreholes in Pasohlávky.

abstract: As the microelectronics industry continues to decrease the size of solder joints, each joint will have to carry a greater current density, making atom diffusion due to current flow, electromigration (EM), a problem of ever-increasing severity. The rate of EM damage depends on current density, operating temperature, and the original microstructure of the solder joint, including void volume, grain orientation, and grain size. While numerous studies have investigated the post-mortem effects of EM and have tested a range of current densities and temperatures, none have been able to analyze how the same joint evolves from its initial to final microstructure. This thesis focuses on the study of EM, thermal aging, and thermal cycling in Sn-rich solder joints. Solder joints were either of controlled microstructure and orientation or had trace alloying element additions. Sn grain orientation has been linked to a solder joints’ susceptibility to EM damage, but the precise relationship between orientation and intermetallic (IMC) and void growth has not been deduced. In this research x-ray microtomography was used to nondestructively scan samples and generate 3D reconstructions of both surface and internal features such as interfaces, IMC particles, and voids within a solder joint. Combined with controlled fabrication techniques to create comparable samples and electron backscatter diffraction (EBSD) and energy-dispersive spectroscopy (EDS) analysis for grain orientation and composition analysis, this work shows how grain structure plays a critical role in EM damage and how it differs from damage accrued from thermal effects that occur simultaneously. Unique IMC growth and voiding behaviors are characterized and explained in relation to the solder microstructures that cause their formation and the possible IMC-suppression effects of trace alloying element addition are discussed. / Dissertation/Thesis / Doctoral Dissertation Materials Science and Engineering 2019

Much of today's high performance computing engines and hand-held mobile devices are products of aggressive CMOS scaling. Technology scaling in semiconductor industry is mainly driven by corresponding improvements in optical lithography technology. Photolithography, the art used to create patterns on the wafer is at the heart of the semiconductor manufacturing process. Lately, improvements in optical technology have been difficult and slow. The transition to deep ultra-violet (DUV) light source (193nm) required changes in lens materials, mask blanks, light source and photoresist. It took more than ten years to develop a stable chemically amplified resist (CAR) for DUV. Consequently, as the industry moves towards manufacturing end-of-the-roadmap CMOS devices, lithography is still based on 193nm light source to print critical dimensions of 45nm, 32nm and likely 22nm. Sub-wavelength lithography creates a number of printability issues. The printed patterns are highly sensitive to topographic changes due to metal planarization, overlay errors, focus and dose variations, random particle defects to name a few. Design for Manufacturability methodologies came into being to help analyze and mitigate manufacturing impacts on the design. Although techniques such as Resolution Enhancement Techniques (RET) which involve optical proximity correction (OPC), phase shift masking (PSM), off-axis illumination (OAI) have been used to greatly improve the printability and better the manufacturing process window, they cannot perfectly compensate for these lithographic deficiencies. DFM methods were primarily devised to predict and correct systematic patterning problems that arise during manufacturing. Apart from systematic errors, random manufacturing variations may occur during photolithography. This is where a statistical approach to modeling of error behavior and its impact on different design parameters may prove to be effective. By incorporating statistical analysis to parameter variation, an effective, non-conservative design can be obtained. IC manufacturing yield is the foremost measure that determines the profitability of a given semiconductor manufacturing process. Thus early prediction of yield detractors is an important step in the design process. Such predictions are based on models, which in turn are rooted in manufacturing process. Success of yield prediction is based on quality of models. The models must capture physical phenomena and yet be efficient for computation. In this work, we present a lithography-based yield model that is computationally practical for use in the design process. The work also provides a methodology to perform statistical lithography rules check to identify hot spots in the design that can contribute to yield loss. Yield recovery methods aimed at minimally modifying the design ultimately produce more printable masks. Apart from IC manufacturing yield, ICs today are vulnerable to various reliability failures including electromigration (EM), negative bias temperature instability (NBTI), hot carrier injection (HCI) and electro-static discharge (ESD). Though such reliability issues have been examined since the beginning of CMOS, manufacturability impacts have created a renewed interest in analyzing them. In this dissertation, we introduce the concept of Design for reliable manufacturability (DFRM) to consider the effect of linewidth changes, gate oxide thickness variations and other manufacturing artifacts. A novel Litho-aware EM calibration and analysis has bee shown in this work. Results indicate that there is a significant difference in EM estimation when litho-predicted layouts are considered during analysis. DFM has always looked at linewidth and material thickness variation as detractors to the design. However, such variations are inevitable. In this work we also consider modeling sensitivity to variations to improve test pattern quality. Test structures sprinkled all over the wafer encounter varying process fluctuations. This can be harnessed to predict the current lithographic process corner which will later be used to choose the test pattern set that results in maximum fault coverage. In summary, the objective of this dissertation is to consider the impact of sub-wavelength lithography on printability and the overall impact on circuit reliability and manufacturing test development.

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