Carbon nanotubes and graphene provide high carrier mobility for ballistic transport, high carrier velocity for fast switching, and excellent mechanical and thermal conductivity. As a result, they are widely considered as next generation candidate materials for nanoelectronics. In this thesis, I first propose a physics-based semi-analytical model for Schottky-barrier (SB) carbon nanotube (CNT) and graphene nanoribbon (GNR) transistors. The model reduces the computational complexity in the two critical but time-consuming steps, namely the calculation of the tunneling probability and the self-consistent evaluation of the surface potential in the transistor channel. Since SB-type CNT and GNR transistors exhibit ambipolar conduction that is not preferable in digital applications, I further propose a semi-analytical model for the double-gate transistor structure that is able to control the ambipolar conduction in-field. Future directions, including the modeling of new CNT and GNR devices and novel circuits based on the in-field controllability of ambipolar conduction, will also be described.

There has been a recent paradigm shift within the wireless communications academic community towards implementation-based algorithm validation. In the past, this task was left to industrial affiliates but in order to close the theory to implementation loop faster research groups are actively developing proof-of-concept demonstrations of their theoretical protocols. In this work we present the Wireless Open-Access Research Platform for Networks (WARPnet) that provides all the computational power and data resources needed to prototype novel physical and MAC layers for emerging technologies. The platform is built to be deployed enabling large-scale network-wide experiments. Scheduling experiments and gathering data can be accomplished with a central server connected to the nodes. We characterize the dedicated control channel built for remote control and statistics aggregation, present frameworks for data transfer and implement example applications that show the methodology for benchmarking distributed wireless experiments.

We introduce a new methodology for post-silicon characterization of the gate-level variations in a manufactured Integrated Circuit (IC). The estimated characteristics are based on the power and the delay measurements that are affected by the process variations. The power (delay) variations are spatially correlated. Thus, there exists a basis in which variations are sparse. The sparse representation suggests using the L1-regularization (the compressive sensing theory). We show how to use the compressive sensing theory to improve post-silicon characterization. We also address the problem by adding spatial constraints directly to the traditional L2-minimization. The proposed methodology is fast, inexpensive, non-invasive, and applicable to legacy designs. Noninvasive IC characterization has a range of emerging applications, including post-silicon optimization, IC identification, and variations' modeling/simulations. The evaluation results on standard benchmark circuits show that, in average, the gate level characteristics estimation accuracy can be improved by more than two times using the proposed methods.

Directional communication has the potential to improve both the energy efficiency of wireless communication without sacrificing its quality. We present a system solution, BeamSwitch, for directional communication on mobile devices. BeamSwitch employs a special multi-antenna system that consists of multiple identical directional antenna or beams, a single regular omni antenna, and a single RF chain. It uses one of the directional beams for transmitting data frames and receiving their acknowledgments and the regular antenna for all other transceiving. BeamSwitch tracks the signal strength of incoming frames and selects the right beam for data transmission. We report an extensive evaluation of BeamSwitch including both measurements with a prototype with three beams and Qualnet-based simulation. Our evaluation shows that BeamSwitch with three 6 dBi directional antennas can improve the energy efficiency of a commercial 802.11 adapter by over 20% and simultaneously provide better or close communication quality. BeamSwitch achieves this under diverse radio propagation environments and extreme mobility (up to 360° per second direction change).

Positron Emission Tomography/Computed Tomography (PET/CT) is a widely used imaging modality for managing patients with cancer. The combination of PET and CT can provide both functional and anatomic information of disease distribution. However, despite its widespread use, it also has some limitations. One drawback is that current PET/CT scanners cannot acquire whole-body scan in a single acquisition but rather has to divide it into multiple sections due to a limitation in the extent of bed travel. The first part of this thesis focuses on developing a software tool that can display multiple PET segments as a single scan to improve the interpretation of these studies. The second part of the thesis focuses on another limitation of PET/CT imaging, namely its low image quality. In this section, an investigation of the correlation between injected dose, patient BMI and scanner design on PET image quality is performed. The objective of this investigation is to determine the significance and extent by which these factors can impact PET image quality. The results of this work can be used as a guide to improve protocol design in an effort to generate an optimal PET image quality.

The need for finding effective means of recycling spectrum is becoming increasingly apparent as the world becomes more crowded with wireless devices. While finding a policy solution to this problem will require years, "cognitive radio" is an immediately applicable technology-based solution. Our attention is focused on how a distributed uncoordinated cognitive group of "secondary" users (those with lower priority access to the spectrum) can push data through its network on a single band and in the presence of non-cognitive "primary" users (those with priority access to the spectrum). The main contribution is a novel class of cognitive radio protocols that accomplish this through feedback, where secondaries estimate residual bandwidth and adapt a performance-based parameter. This class of solutions is presented, its parameters are explored and a specific implementation is demonstrated with insights gained.

Cooperation among radios in wireless networks has been shown to improve communication in several aspects. We analyze a wireless network which employs multiple parallel relay transceivers to assist in communication between a single source-destination pair, demonstrating that gains are achieved when a random subset of relays is selected. We derive threshold values for the received signal-to-noise ratios (SNRs) at the relays based on outage probabilities; these thresholds essentially determine the active subset of relays in each time frame for our parallel relay network; due the random nature of wireless channels, this active subset is a random. Two established forwarding protocols for the relays, Amplify-and-Forward and Decode-and-Forward, are combined to create a hybrid relaying protocol which is analyzed in conjunction with both regenerative coding and distributed space-time coding at the relays. Finally, the allocation of power resources to minimize the end-to-end probability of outage is considered.

<p>The relentless scaling of semiconductor devices and high integration levels have lead to a steady increase in the cost of manufacturing test for integrated circuits (ICs). The higher test cost leads to an increase in the product cost of ICs. Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of a variety of core-based system-on-chip (SoC) designs. Packaging has also been recognized as a significant contributor to the product cost for SoCs. Packaging cost and the test cost for packaged chips can be reduced significantly by the use of effective test methods at the wafer level, also referred to as wafer sort. </p><p>Test application time is a major practical constraint for wafer sort, even more than for package test. Therefore, not all the scan-based digital test patterns can be applied to the die under test. This thesis first presents a test-length selection technique for wafer-level testing of core-based SoCs. This optimization technique, which is based on a combination of statistical yield modeling and integer linear programming (ILP), provides the pattern count for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. A large number of wafer-probe contacts can potentially lead to higher yield loss during wafer sort. An optimization framework is therefore presented to address test access mechanism (TAM) optimization and test-length selection for wafer-level testing, when constraints are placed on the number of number of chip pins that can be contacted. </p><p>Next, a correlation-based signature analysis technique is presented for mixed-signal test at the wafer-level using low-cost digital testers. The proposed method overcomes the limitations of measurement inaccuracies at the wafer-level. A generic cost model is developed to evaluate the effectiveness of wafer-level testing of analog and digital cores in a mixed-signal SoC, and to study its impact on test escapes, yield loss and packaging cost. Results are presented for a typical mixed-signal "big-D/small-A" SoC from industry, which contains a large section of flattened digital logic and several large mixed-signal cores.</p><p>Wafer-level test during burn-in (WLTBI) is an emerging practice in the semiconductor industry that allows testing to be performed simultaneously with burn-in at the wafer-level. However, the testing of multiple cores of a SoC in parallel during WLTBI leads to constantly-varying device power during the duration of the test. This power variation adversely affects predictions of temperature and the time required for burn-in. A test-scheduling technique is presented for WLTBI of core-based SoCs, where the primary objective is to minimize the variation in power consumption during test. A secondary objective is to minimize the test application time. </p><p>Finally, this thesis presents a test-pattern ordering technique for WLTBI. The objective here is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is solved using ILP and efficient heuristic techniques. The thesis also demonstrates how test-pattern manipulation and pattern-ordering can be combined for WLTBI. Test-pattern manipulation is carried out by carefully filling the don't-care (X) bits in test cubes. The X-fill problem is formulated and solved using an efficient polynomial-time algorithm. </p><p>In summary, this research is targeted at cost-efficient wafer-level test and burn-in of current- and next-generation semiconductor devices. The proposed techniques are expected to bridge the gap between wafer sort and package test, by providing cost-effective wafer-scale test solutions. The results of this research will lead to higher shipped-product quality, lower product cost, and pave the way for known good die (KGD) devices, especially for emerging technologies such as three-dimensional integrated circuits.</p> / Dissertation

<p>Microfluidics-based biochips combine electronics with biochemistry to open new application areas such as point-of-care medical diagnostics, on-chip DNA analysis, automated drug discovery and protein crystallization. Bioassays can be mapped to microfluidic arrays using synthesis tools and they can be executed through the electronic manipulation of sample and reagent droplets. The 2007 International Technology Roadmap for Semiconductors articulates the need for innovations in biochip and microfluidics as part of functional diversification ("Higher Value Systems" and "More than Moore"). This document also highlights "Medical" as being a System Driver for 2009 This thesis envisions an automated design flow for microfluidic biochips, in the same way as design automation revolutionized IC design in the 80s and 90s. Electronic design-automation techniques are leveraged whenever possible, and new design-automation solutions are developed for problems that are unique to digital microfluidics. Biochip users (e.g., chemists, nurses, doctors and clinicians) and the biotech/pharmaceutical industry will adapt more easily to new technology if appropriate design tools and in-system automation methods are made available. The thesis is focused on a design automation framework that addresses optimization problems related to layout, synthesis, droplet routing, testing, and testing for digital microfluidic biochips. Optimization goal includes the minimization of time-to-response, chip area, and test complexity. The emphasis here is on practical issues such as defects, fabrication cost, physical constraints, and application-driven design. To obtain robust, easy-to-route chip designs, a unified synthesis method has been developed to incorporate droplet routing and defect tolerance in architectural synthesis and physical design. It allows routing-aware architectural-level design choices and defect-tolerant physical design decisions to be made simultaneously. v In order to facilitate the manufacture of low-cost and disposable biochips, design methods that rely on a small number of control pins have also been developed. Three techniques have been introduced for the automated design of such pin-constraint biochips. First, a droplet-trace-based array partitioning method has been combined with an efficient pin assignment technique, referred to as the "Connect-5 algorithm". The second pin-constrained design method is based on the use of "rows" and "columns" to access electrodes. An efficient droplet manipulation method has been developed for this cross-referencing technique. The method maps the droplet-movement problem to the clique-partitioning problem from graph theory, and it allows simultaneous movement of a large number of droplets on a microfluidic array. The third pin-constrained design technique is referred to as broadcast-addressing. This method provides high throughput for bioassays and it reduces the number of control pins by identifying and connecting control pins with "compatible" actuation sequences. Dependability is another important attribute for microfluidic biochips, especially for safety-critical applications such as point-of-care health assessment, air-quality monitoring, and food-safety testing. Therefore, these devices must be adequately tested after manufacture and during bioassay operations. This thesis presents a cost-effective testing method, referred to as "parallel scan-like test", and a rapid diagnosis method based on test outcomes. The diagnosis outcome can be used for dynamic reconfiguration, such that faults can be easily avoided, thereby enhancing chip yield and defect tolerance. The concept of functional test for digital biochip has also been introduced for the first time in this thesis. Functional test methods address fundamental biochip operations such as droplet dispensing, droplet transportation, mixing, splitting, and capacitive sensing. To facilitate the application of the above testing methods and to increase their effectiveness, the concept of design-for-testability (DFT) for microfluidic biochips has been introduced in this thesis. A DFT method has been proposed that incorporates a test plan into vi the fluidic operations of a target bioassay protocol. The above optimization tools have been used for the design of a digital microfluidic biochip for protein crystallization, a commonly used technique to understand the structure of proteins. An efficient solution-preparation algorithm has been developed to generate a solution-preparation plan that lists the intermediate mixing steps needed to generate target solutions with the required concentrations. A multi-well high-throughput digital microfluidic biochip prototype for protein crystallization has also been designed. In summary, this thesis research has led to a set of practical design tools for digital microfluidics. A protein crystallization chip has been designed to highlight the benefits of this automated design flow. It is anticipated that additional biochip applications will also benefit from these optimization methods.</p> / Dissertation

Dissertation