No / Continuously identifying a user’s location context provides new opportunities to understand daily life and human behavior. Indoor location systems have been mainly based on WiFi infrastructures which consume a great deal of energy mostly due to keeping the user’s WiFi device connected to the infrastructure and network communication, limiting the overall time when a user can be tracked. Particularly such tracking systems on battery-limited mobile devices must be energy-efficient to limit the impact on the experience of using a phone. Recently, there have been a lot of studies of energy-efficient positioning systems, but these have focused on outdoor positioning technologies. In this paper, we propose a novel indoor tracking framework that intelligently determines the location sampling rate and the frequency of network communication, to optimize the accuracy of the location data while being energy-efficient at the same time. This framework leverages an accelerometer, widely available on everyday smartphones, to reduce the duty cycle and the network communication frequency when a tracked user is moving slowly or not at all. Our framework can work for 14 h without charging, supporting applications that require this location information without affecting user experience.

The operational life of wireless sensor network based distributed sensing systems is limited by the energy provided by a portable battery pack. Owing to the inherently resource constrained nature of wireless sensor networks and nodes, a major research thrust in this field is the search for energy-aware methods of operation. Communication is among the most energy-intensive operations on a wireless device. It is therefore, the focus of our efforts to develop an energy-aware method of communication and to introduce a degree of reconfigurability to ensure autonomous operation of such devices. Given this background, three research tasks have been identified and investigated during the course of this research. 1) Devising an energy-efficient method of communication in a framework of reconfigurable operation: The dependence of the energy consumed during communication on the number of bits transmitted (and received) was identified from prior research work. A novel method of data compression was designed to exploit this dependence. This method uses the time-limited, orthonormal Walsh functions as basis functions for representing signals. The L2 norm of this representation is utilized to further compress the signals. From Parseval’s relation, the square of the L2 norm represents the energy content of a signal. The application of this theorem to our research makes it possible to use the L2 norm as a control knob. The operation of this control knob makes it possible to optimize the number of terms required to represent signals. The time-limited nature of the Walsh functions was leveraged to inject dynamic behaviour into our coding method. This time-limited nature allows decomposition of finite time-segments, without attendant limitations like loss of resolution that are inherent to derived, discrete transforms like the discrete Fourier transform or the discrete time Fourier transform. This decomposition over successive, finite time-segments, coupled with innovative operation of the previously mentioned control knob on every segment, gives us a dynamic scaling technique. The amount of data to be transmitted is in turn based on the magnitude of the coefficients of decomposition of each time-segment, leading to the realization of a variable word length coding method. This dynamic coding method can identify evolving changes or events in the quantity being sensed. The coefficients of decomposition represent features present in successive time-segments of signals and therefore enable identification of evolving events. The ability to identify events as they occur enables the algorithm to react to events as they evolve in the system. In other words the data transmission and the associated energy consumption are imparted a reconfigurable, event-driven nature by implementation of the coding algorithm. Performance evaluation of this method via simulations on machine generated (bearing vibration) and biometric (electro-cardio gram) signals shows it be a viable method for energy-aware communication. 2) Developing a framework for reconfigurable triggering: A framework for completely autonomous triggering of the coding method has been developed. This is achieved by estimating correlations of the signal with the representative Walsh functions. The correlation coefficient of a signal segment with a Walsh function gives a picture of the amount of energy localized by the function. This information is used to autonomously tune the abovementioned control knob or, in more proper terms, the degree of thresholding used in compression. Evaluation of this framework on bearing vibration and electro-cardio gram signals has shown results consistent with those of previous simulations. 3) Devising a computationally compact method of feature classification: A method of investigating time series measurements of dynamic systems in order to classify features buried in the signal measurements was investigated. The approach involves discretizing time-series measurements into strings of pre-defined symbols. These strings are transforms of the original time-series measurements and are a representation of the system dynamics. A method of statistically analyzing the symbol strings is presented and its efficacy is studied through representative simulations and experimental investigation of vibration signals recorded from a rolling bearing element. The method is computationally compact because it obviates the need for local signal processing tasks like denoising, detrending and amplification. Results indicate that the method can effectively classify deteriorating machine health, changing operating conditions and evolving defects. In addition to these major foci, another research task was the design and implementation of a wireless network testbed. This testbed consists of a network of netbooks, connected together wirelessly and was utilized for experimental verification of the variable word length coding method.

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In the past, we could rely on technology scaling and new micro-architectural techniques to improve the performance of processors. Nowadays, both of these methods are reaching their limits. The primary concern in future architectures with billions of transistors on a chip and limited power budgets is power/energy efficiency. Full-custom design of application-specific cores can yield up to two orders of magnitude better power efficiency over conventional general-purpose cores. However, a tremendous design effort is required in integrating a new accelerator for each new application. In this dissertation, we present the design of specialized compute fabrics that maintain the efficiency of full custom hardware while providing enough flexibility to execute a whole class of coarse-grain operations. The broad vision is to develop integrated and specialized hardware/software solutions that are co-optimized and co-designed across all layers ranging from the basic hardware foundations all the way to the application programming support through standard linear algebra libraries. We try to address these issues specifically in the context of dense linear algebra applications. In the process, we pursue the main questions that architects will face while designing such accelerators. How broad is this class of applications that the accelerator can support? What are the limiting factors that prevent utilization of these accelerators on the chip? What is the maximum achievable performance/efficiency? Answering these questions requires expertise and careful codesign of the algorithms and the architecture to select the best possible components, datapaths, and data movement patterns resulting in a more efficient hardware-software codesign. In some cases, codesign reduces complexities that are imposed on the algorithm side due to the initial limitations in the architectures. We design a specialized Linear Algebra Processor (LAP) architecture and discuss the details of mapping of matrix-matrix multiplication onto it. We further verify the flexibility of our design for computing a broad class of linear algebra kernels. We conclude that this architecture can perform a broad range of matrix-matrix operations as complex as matrix factorizations, and even Fast Fourier Transforms (FFTs), while maintaining its ASIC level efficiency. We present a power-performance model that compares state-of-the-art CPUs and GPUs with our design. Our power-performance model reveals sources of inefficiencies in CPUs and GPUs. We demonstrate how to overcome such inefficiencies in the process of designing our LAP. As we progress through this dissertation, we introduce modifications of the original matrix-matrix multiplication engine to facilitate the mapping of more complex operations. We observe the resulting performance and efficiencies on the modified engine using our power estimation methodology. When compared to other conventional architectures for linear algebra applications and FFT, our LAP is over an order of magnitude better in terms of power efficiency. Based on our estimations, up to 55 and 25 GFLOPS/W single- and double-precision efficiencies are achievable on a single chip in standard 45nm technology. / text