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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
1

Low-cost assertion-based fault tolerance in hardware and software

Vemu, Ramtilak, January 1900 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.
2

A new approach for improving system availability

Lam, Kwok-yan January 1991 (has links)
No description available.
3

Fully interconnected fault tolerant transputer networks using global link adaptors

Hossack, C. J. January 1995 (has links)
No description available.
4

Distributed recovery in fault-tolerant interconnected networks

Mohammadi, Shahram January 1990 (has links)
No description available.
5

Optoelectronic neural networks

Allen, T. J. January 1996 (has links)
No description available.
6

Threshold analysis with fault-tolerant operations for nonbinary quantum error correcting codes

Kanungo, Aparna 01 November 2005 (has links)
Quantum error correcting codes have been introduced to encode the data bits in extra redundant bits in order to accommodate errors and correct them. However, due to the delicate nature of the quantum states or faulty gate operations, there is a possibility of catastrophic spread of errors which might render the error correction techniques ineffective. Hence, in this thesis we concentrate on how various operations can be carried out fault-tolerantly so that the errors are not propagated in the same block. We prove universal fault-tolerance for nonbinary CSS codes. This thesis is focussed only on nonbinary quantum codes and all the results pertain to nonbinary codes. Efficient error detection and correction techniques using fault-tolerant techniques can help as long as we ensure that the gate error probability is below a certain threshold. The calculation of this threshold is therefore important to see if quantum computations are realizable or not, even with fault-tolerant operations. We derive an expression to compute the gate error threshold for nonbinary quantum codes and test this result for different classes of codes, to get codes with best threshold results.
7

Fault tolerant multipliers and dividers using time shared triple modular redundancy /

Gallagher, William Lynn, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 139-145). Available also in a digital version from Dissertation Abstracts.
8

Byzantine fault-tolerance and beyond

Martin, Jean-Philippe Etienne 28 August 2008 (has links)
Not available / text
9

Co-design of Fault-Tolerant Systems with Imperfect Fault Detection

Chen, Yi-Ching January 2014 (has links)
In recent decades, transient faults have become a critical issue in modernelectronic devices. Therefore, many fault-tolerant techniques have been proposedto increase system reliability, such as active redundancy, which can beimplemented in both space and time dimensions. The main challenge of activeredundancy is to introduce the minimal overhead of redundancy and to schedulethe tasks. In many pervious works, perfect fault detectors are assumed to simplifythe problem. However, the induced resource and time overheads of suchfault detectors make them impractical to be implemented. In order to tacklethe problem, an alternative approach was proposed based on imperfect faultdetectors. So far, only software implementation is studied for the proposed imperfectfault detection approach. In this thesis, we take hardware-acceleration intoconsideration. Field-programmable gate array (FPGA) is used to accommodatetasks in hardware. In order to utilize the FPGA resources efficiently, themapping and the selection of fault detectors for each task replica have to be carefullydecided. In this work, we present two optimization approaches consideringtwo FPGA technologies, namely, statically reconfigurable FPGA and dynamicallyreconfigurable FPGA respectively. Both approaches are evaluated andcompared with the proposed software-only approach by extensive experiments.
10

Reliability issues in the design of distributed object-based architectures

Mancini, Luigi Vincenzo January 1989 (has links)
This thesis is aimed at enhancing the existing set of techniques for building distributed systems, specifically from the point of view of fault-tolerant com- puting. Reliability is of fundamental importance in the design and operation of dis- tributed systems, as an increasing number of computers are employed in the automation of various essential services. In the past decade, much research effort has been concerned with the object-based methodology for the design and implementation of reliable distributed systems. This thesis describes three contributions to this effort. First, it is shown that object-based programming features can in fact be introduced into pro- cedural languages provided that these languages are endowed with certain facilities. Then, work is discussed which illustrates the relationship between distributed object-based architectures and an apparently different form of distributed architectures based on processes. This work puts the notion of object-based architectures into a new perspective, which shows that the object-based philosophy and the process-based philosophy are the dual of each other. Finally, an important aspect of the design of an object-based distributed architecture is investigated, that of automatic garbage collection. A distri- buted garbage collection scheme is described that handles fault tolerance by an extension of the technique commonly employed to detect unwanted com- putations in distributed architectures. The scheme proposed can also be seen as yet a further illustration of the link between object-based and process-based architectures.

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