Thesis (M.S.)--State University of New York at Binghamton, Electrical Engineering Dept., 2006. / Includes bibliographical references.

Modular Multiplication is a time-consuming arithmetic operation because it involves multiplication as well as division. Modular exponentiation can be performed as a sequence of modular multiplications. Speeding the modular multiplication increases the speed of modular exponentiation. Modular exponentiation and modular multiplication are heavily used in current cryptographic systems. Well-known cryptographic algorithms, such as RSA and Diffie-Hellman key exchange, require modular exponentiation operations. Elliptic curve cryptography (ECC) needs modular multiplication. Information security is increasingly becoming very important. Encryption and Decryption are very likely to be in many systems that exchange information to secure, verify, or authenticate data. Many systems, like the Internet, cellular phones, hand-held devices, and E-commerce, involve private and important information exchange and they need cryptography to make it secure. There are three possible solutions to accomplish the cryptographic computation: software, hardware using application-specific integrated circuits (ASICs), and hardware using field-programmable gate arrays (FPGAs). The software solution is the cheapest and most flexible one. But, it is the slowest. The ASIC solution is the fastest. But, it is inflexible, very expensive, and needs long development time. The FPGA solution is flexible, reasonably fast, and needs shorter development time. Montgomery multiplication algorithm is a very smart and efficient algorithm for calculating the modular multiplication. It replaces the division by a shift and modulus-addition (if needed) operations, which are much faster than regular division. The algorithm is also very suitable for a hardware implementation. Many designs have been proposed for fixed precision operands. A word-based algorithm and the scalable Montgomery multiplier based on this algorithm have been proposed later. The scalable multiplier can be configured to meet the design area-time tradeoff. Also, it can work for any operand precision up to the memory capacity. In this thesis, we develop a prototyping environment that can be used to verify the functionality of the scalable Montgomery multiplier on the circuit level. All the software, hardware, and firmware components of this environment will be described. Also, we will discuss how this environment can be used to develop cryptographic applications or test procedures on top of it. We also present two FPGA designs of the processing unit of the scalable Montgomery multiplier. The FPGA design techniques that have been used to optimize these designs are described. The implementation results are analyzed and the designs are compared against each other. The FPGA implementation of the first design is also compared against its ASIC implementation. / Graduation date: 2003

Thesis (M. Sc.)--University of Alberta, 2009. / Title from PDF file main screen (viewed on Dec. 14, 2009). "A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Science, Department of Electrical and Computer Engineering, University of Alberta." Includes bibliographical references.

Thesis (M.S.)--University of Florida, 2002. / Title from title page of source document. Includes vita. Includes bibliographical references.

Title from PDF of title page (University of Missouri--Columbia, viewed on Feb 18, 2010). The entire thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file; a non-technical public abstract appears in the public.pdf file. Thesis advisor: Dr. Harry Tyrer. Includes bibliographical references.

Thesis (M. Eng. Sc.)--University of Queensland, 2002. / Includes bibliographical references.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 219-224). Also available online.

The era of big data has led to problems of unprecedented scale and complexity that are challenging the computing capability of conventional computer systems. One way to address the computational and communication challenges of such demanding applications is to incorporate the use of non-conventional hardware accelerators such as FPGAs into existing systems. By providing a mix of FPGAs and conventional CPUs as computing resources in a heterogeneous cluster, a distributed computing environment can be achieved to address the need of both compute-intensive and data-intensive applications. However, utilizing heterogeneous clusters requires application developers’ comprehensive knowledge on both hardware and software. In order to assist programmers to take advantage of the synergy between hardware and software easily, an easy-to-use framework for virtualizing the underlying FPGA computing resources of the heterogeneous cluster is motivated. In this work, a heterogeneous cluster consisting of both FPGAs and CPUs was built and a framework for managing multiple FPGAs across the cluster was designed. The major contribution of the framework is to provide an abstraction layer between the application developer and the underlying FPGA computing resources, so as to improve the overall design productivity. An inter-FPGA communication system was implemented such that gateware executing on FPGAs can communicate with each other autonomously to the CPU. Furthermore, to demonstrate a real-life application on the heterogeneous cluster, a generic k-means clustering application was implemented, using the MapReduce programming model. The implementation of the k-means application on multiple FPGAs was compared with a software-only version that was run on a Hadoop multi-core computer cluster. The performance results show that the FPGA version outperforms the Hadoop version across various parameters. An in-depth study on the communication bottleneck presented in the system was also carried out. A number of experiments were specifically designed to benchmark the performance of each I/O channel. The study shows that the major source of I/O bottleneck lies at the communication between the host system and the FPGA. This gives insight into programming considerations of potential applications on the cluster as well as improvement to the framework. Moreover, the benefit of multiple FPGAs was investigated through a series of experiments. Compared with putting all mappers on a single FPGA, it was found that distributing the same amount of mappers across more FPGAs can provide a tradeoff between FPGA resources and I/O performance. / published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

No description available.