Thèse doct. d'État--Lettres--Paris III, 1977. / Bibliogr. p. 251-264.

Inaug-Diss.--Halle-Wittenberg. / "Lebenslauf": 1 l. at end. "Texte und Quellen": p. [7]-9.

The main goal of this project is to present my investigation of finite images of the progenitor 2^(*n) : N for various N and several values of n. We construct each image by using the technique of double coset enumeration and give a proof of the isomorphism type of the image. We obtain the group 7^2: D_6 as a homomorphic image of the progenitor 2^(*14) : D_14, we obtain the group 2^4 : (5 : 4) as a homomorphic image of the progenitor 2^(*5) : (5 : 4), we obtain the group (10 x10) : ((3 x 4) : 2) as a homomorphic image of the progenitor 2^(*15) : (15x4), we obtain the group PGL(2; 7) as a homomorphic image of the progenitor 2^7 : D_14, we obtain the group S_6 as a homomorphic image of the progenitor 2^5 : (5 : 4), and we obtain the group S_7 as a homomorphic image of the progenitor 2^(*15) : (15 : 4). Also, have given some unsuccessful progenitors.

Thesis--University of Dacca. / Bibliography: p. [174]-180.

Inaug.-Diss.--Munich, 1965. / Vita. Bibliography: [104-106].

Texte remanié de: Doct-diss.--Philos.--Evanston, Northwestern university's graduate school, 1979. / Bibliogr. p. 224-228. Index.

M.A. / Coming to terms with the challenge of modernity has been a major concern for Muslim scholars. Faced with the reality of the global system of nation states, and the question that the challenges of secularism, democracy and religious pluralism pose for a traditional understanding of Islâm, many contemporary Muslim scholars have sought to develop new visions of their faith in order to engage seriously with these concerns. This dissertation looks at the writings of the Indian âlim, Sayyid Abul Hasan `Ali Nadwi, who has developed an incisive approach to the challenges of da`wah and dialogue Muslims globally and Indian Muslims particularly are faced with. This study examines how he as a member of the Muslim minority in India, has sought to present Islâm in terms that are intelligent to the modern mind, as well as making it possible for Muslims in India to attempt to create a balance as loyal citizens of the state, on the one hand, and as practising believers of their religion, on the other. Furthermore this vision is given a global dimension for Muslims living in the West where the challenges are not dissimilar from the Indian context. / Prof. J.F.J. van Rensburg

The main motivation of the Compact Muon Solenoid (CMS) experiment is to explore and to discover physics underlying electro-weak asymmetry breaking. Beside this, CMS detector provides an opportunity to do various experiments for detecting new physics signatures beyond the Standard Model (SM). Investigation of these signatures requires the identification and precise energy and moment measurement of electrons, muons, photons, and jets. The objective of this thesis is the calculation of the efficiencies for the measurement of W charge asymmetry in inclusive pp→W (μυ) production. The charge asymmetry is defined to be the difference between W^+ and W^- bosons, normalized to the sum. This asymmetry is sensitive to the u-quark and d-quark ratios in the proton and precise measurement of the W charge asymmetry can provides new insights to the proton structure functions. Therefore, to improve understanding of SM backgrounds in search for new physics, the moun trigger, isolation, reconstruction, identification efficiencies has been studied using partial data collected by the CMS detector during pp collisions at the LHC in 2011. The dataset corresponds to an integrated luminosity of 2.31 fb-1. The efficiencies are measured as functions of the decay muon pseudo rapidity and transverse momentum based on "tag and probe" method. The efficiency measurements are compared to their estimated value from the Monte Carlo simulations so as to provide scaling factors to correct to the residual mis-modeling of the CMS muon performance. The comparison with simulations based on MC simulations opens a gate for validation of the detector simulation and optimization of selection strategies.

The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data integrity is achieved by chaining Galois field multiplication operations while a symmetric key block cipher such as the Advanced Encryption Standard (AES), is used to meet goals of confidentiality. Area optimization in a number of proposed high throughput GCM designs have been approached through implementing efficient composite Sboxes for AES. Not as much work has been done in reducing area requirements of the Galois multiplication operation in the GCM which consists of up to 30% of the overall area using a bruteforce approach. Current pipelined implementations of GCM also have large key change latencies which potentially reduce the average throughput expected under traditional internet traffic conditions. This thesis aims to address these issues by presenting area efficient parallel multiplier designs for the GCM and provide an approach for achieving low latency key changes. The widely known Karatsuba parallel multiplier (KA) and the recently proposed Fan-Hasan multiplier (FH) were designed for the GCM and implemented on ASIC and FPGA architectures. This is the first time these multipliers have been compared with a practical implementation, and the FH multiplier showed note worthy improvements over the KA multiplier in terms of delay with similar area requirements. Using the composite Sbox, ASIC designs of GCM implemented with subquadratic multipliers are shown to have an area savings of up to 18%, without affecting the throughput, against designs using the brute force Mastrovito multiplier. For low delay LUT Sbox designs in GCM, although the subquadratic multipliers are a part of the critical path, implementations with the FH multiplier showed the highest efficiency in terms of area resources and throughput over all other designs. FPGA results similarly showed a significant reduction in the number of slices using subquadratic multipliers, and the highest throughput to date for FPGA implementations of GCM was also achieved. The proposed reduced latency key change design, which supports all key types of AES, showed a 20% improvement in average throughput over other GCM designs that do not use the same techniques. The GCM implementations provided in this thesis provide some of the most area efficient, yet high throughput designs to date.

The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data integrity is achieved by chaining Galois field multiplication operations while a symmetric key block cipher such as the Advanced Encryption Standard (AES), is used to meet goals of confidentiality. Area optimization in a number of proposed high throughput GCM designs have been approached through implementing efficient composite Sboxes for AES. Not as much work has been done in reducing area requirements of the Galois multiplication operation in the GCM which consists of up to 30% of the overall area using a bruteforce approach. Current pipelined implementations of GCM also have large key change latencies which potentially reduce the average throughput expected under traditional internet traffic conditions. This thesis aims to address these issues by presenting area efficient parallel multiplier designs for the GCM and provide an approach for achieving low latency key changes. The widely known Karatsuba parallel multiplier (KA) and the recently proposed Fan-Hasan multiplier (FH) were designed for the GCM and implemented on ASIC and FPGA architectures. This is the first time these multipliers have been compared with a practical implementation, and the FH multiplier showed note worthy improvements over the KA multiplier in terms of delay with similar area requirements. Using the composite Sbox, ASIC designs of GCM implemented with subquadratic multipliers are shown to have an area savings of up to 18%, without affecting the throughput, against designs using the brute force Mastrovito multiplier. For low delay LUT Sbox designs in GCM, although the subquadratic multipliers are a part of the critical path, implementations with the FH multiplier showed the highest efficiency in terms of area resources and throughput over all other designs. FPGA results similarly showed a significant reduction in the number of slices using subquadratic multipliers, and the highest throughput to date for FPGA implementations of GCM was also achieved. The proposed reduced latency key change design, which supports all key types of AES, showed a 20% improvement in average throughput over other GCM designs that do not use the same techniques. The GCM implementations provided in this thesis provide some of the most area efficient, yet high throughput designs to date.