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<p> High Level Synthesis (HLS) is a promising approach to managing design complexity at a more abstract level as integrated circuit technology edges deeper into sub-micron design. One useful facet of HLS is the ability to automatically integrate architectural components that can address potential reliability issues, which may be on the increase due to miniaturization. Research into harnessing HLS for fault tolerance (FT) has been progressing since the early 1990's. There currently exists a large body of work regarding methods to incorporate capabilities such as fault detection, compensation, and recovery into HLS design.</p> <p> While many avenues of FT have been explored in the HLS environment, very little work has considered the effectiveness and feasibility of these techniques in the context of large HLS systems, which presumably is the raison d'etre of HLS. While existing HLS FT approaches are often elegant and involve highly sophisticated techniques to achieve optimal solutions, the costs of HLS infrastructure in regards to scalability are not well reported. The intent of this thesis is to explore the ramifications of applying common HLS techniques to large designs.</p> <p> Furthermore, a new HLS tool entitled RIFT is presented that is specifically designed to mitigate infrastructure costs that mount as greater parallelism is utilized. RIFT is named for its design philosophy of "Reducing Interconnects for Fault Tolerance". RIFT iteratively builds a logical hardware representation, which consists of both the components instantiated and their interconnections, one operation at a time. It chooses the next operation to be "mapped" to the burgeoning design based on scheduling constraints as well as the extra hardware and interconnect costs required to support a particular selection. Emphasis is placed on minimizing the delay of the datapath in effort to reduce the performance cost associated with the extra interconnects needed for FT. RIFT has been used to generate efficient solutions for FT designs requiring as many as a thousand operations.</p> / Thesis / Master of Applied Science (MASc)

A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test time. Hence, those methods do not render exploration of a large design space, which may result in a local optimum. In this thesis, we present three methods, which aim to address the problem. The first method tries to find a register assignment for each k-test session in a heuristic manner, where k=1,2,…,N and N is the number of modules of the circuit. Therefore, it offers a range of designs with different figures of merit in area and test time. The second method is based on integer linear programming (ILP). The proposed ILP based method performs the three tasks, assignments of registers, interconnections, and BIST registers, concurrently to yield optimal or near-optimal designs. We describe a complete set of ILP formulations for the three tasks. The ILP based method achieves optimal solutions for most circuits in hardware overhead, but it takes long processing time. The third method, the region-wise heuristic method. It partitions a given data flow graph into smaller regions based on control steps and applies the ILP to each region successively to reduce the processing time. To measure the performance of BIST accurately and to demonstrate the practicality of our BIST synthesis method, we implemented a DSP circuit; an 8x8 two-dimensional discrete cosine transform (DCT) processor. We implemented two versions of the algorithm, one with incorporation of our BIST method and the other without BIST, to verify the validity of our simplified cost model to estimate BIST area overhead. The two major parts of the circuit, data path and controller, were synthesized using our high-level BIST synthesis tool. All the circuits are implemented and laid out using an ASIC design flow developed at Virginia Tech. Experimental results show that the three proposed high-level BIST synthesis methods perform better than or comparable to existing BIST synthesis systems. They indeed yield various designs that enable users to trade between area overhead and test time. The region-wise heuristic method reduces the processing time by several orders of magnitude, while the quality of the solution is slightly compromised compared with the ILP-based optimal method. The implementation of DCT circuits demonstrate that our method is applicable to industry size circuits, and the BIST area overhead measured at the layout is close to the estimated one. / Ph. D.

The ever-growing competition in current electronics industry has resulted in stringent time-to-market goals and reduced design time available to engineers. Lesser design time has subsequently raised a need for high-level synthesis design methodologies that raise the design to a higher level of abstraction. Higher level of abstraction helps in increasing the predictability and productivity of the design and reduce the number of bugs due to human-error. It also enables the designer to try out dierent optimization strategies early in the design stage. In-spite of all these advantages, high-level synthesis design methodologies have not gained much popularity in the mainstream design flow mainly because of the reasons like lack of readability and reliability of the generated register transfer level (RTL) code. The compiler framework presented in this thesis allows the user to draw high-level graphical models of the system. The compiler translates these models into synthesizeable RTL Verilog designs that exhibit their desired functionality following communicating sequential processes (CSP) model of computation. CSP model of computation introduces a good handshaking mechanism between different components in the design that makes designs less prone to timing violations during implementation and bottlenecks while in actual operation. / Master of Science

Computer vision technology can be seen in a variety of applications ranging from mobile phones to autonomous vehicles. Many computer vision applications such as drones and autonomous vehicles requires real-time processing capability in order to communicate with the control unit for sending commands in real time. Besides real-time processing capability, it is crucial to keep the power consumption low in order to extend the battery life of not only mobile devices, but also drones and autonomous vehicles. FPGAs are desired platforms that can provide high-performance and low-power solutions for real-time video processing. As hardware designs typically are more time consuming than equivalent software designs, this thesis proposes a rapid prototyping flow for FPGA-based video processing system design by taking advantage of the use of high performance AXI interface and a high level synthesis tool, Vivado HLS. Vivado HLS provides the convenience of automatically synthesizing a software implementation to hardware implementation. But the tool is far from being perfect, and users still need embedded hardware knowledge and experience in order to accomplish a successful design. In order to effectively create a stream type video processing system as well as to utilize the fastest memory on an FPGA, a sliding window memory architecture is proposed. This memory architecture can be applied to a series of video processing algorithms while the latency between an input pixel and an output pixel is minimized. By comparing my approach with other works, this optimized memory architecture proves to offer better performance and lower resource usage over what other works could offer. Its reconfigurability also provides better adaptability of other algorithms. In addition, this work includes performance and power analysis among an Intel CPU based design, an ARM based design, and an FPGA-based embedded design. / Master of Science

As the rate and severity of malicious software attacks have escalated, industrial control systems (ICSes) have emerged as a particularly vulnerable target. ICSes govern the automation of the physical processes in industries such as power, water, oil and manufacturing. In contrast to the personal computing space, where attackers attempt to capture information or computing resources, the attacks directed at ICSes aim to degrade or destroy the physical processes or plants maintained by the ICS. Exploits with potentially catastrophic results are sold on brokerages to any interested party. Previous efforts in ICS security implicitly and mistakenly trust internal software. This thesis presents an architecture for trust enhancement of critical embedded processes (TECEP). TECEP assumes that all software can be or has already been compromised. Trust is instead placed in hardware that is invisible to any malicious software. Software processes critical for stable operation are duplicated in hardware, along with a supervisory process to monitor the behavior of the plant. Furthermore, a copy of the software and a model of the plant are implemented in hardware in order to estimate the system's future behavior. In the event of an attack, the hardware can successfully identify the plant's abnormal behavior in either the present or the future and supersede the software's directives, allowing the plant to continue functioning correctly. This approach to ICS security can be retrofitted to existing ICSes, has minimal impact on the ICS design process, and modestly increases hardware requirements in a programmable system-on-chip. / Master of Science

The phenomenal density growth in semiconductors has resulted in the availability of billions of transistors on a single die. The time-to-design is shrinking continuously due to aggressive competition. Also, the integration of many discrete components on a single chip is growing at a rapid pace. Designing such heterogeneous systems in short duration is becoming difficult with existing technology. Field-Programmable Gate Arrays offer a good alternative in both productivity and heterogeneity issues. However, there are many obstacles that need to be addressed to make them a viable option. One such obstacle is the lack of early design space exploration tools and techniques for FPGA designs. This thesis develops techniques to evaluate systematically, the available design options before the actual system implementation. The aspect which makes this problem interesting, yet complicated, is that a system-level optimization is not linearly summable. The discrete components of a system, benchmarked as best in all design parameters — speed, area and power, need not add up to the best possible system. This work addresses the problem in two ways. In the first approach, we demonstrate that by working at higher levels of abstraction, one can achieve orders of improvement in productivity. Designing a system directly from its behavioral description is an on-going effort in industry. Instead of focusing on design aspects, we use these methods to develop quick prototypes and estimate the design parameters. Design space exploration needs relative comparison among available choices and not accurate values of design parameters. It is shown that the proposed method can do an acceptable job in this regard. The second approach is about evolving statistical techniques for estimating the design parameters and then algorithmically searching the design space. Specifically, a high level power estimation model is developed for FPGA designs. While existing techniques develop power model for discrete components separately, this work evaluates the option of generic power model for multiple components. / Master of Science

Modern systems fulfil calculation tasks across the hardware- software boundary. Tasks are divided into coarse parallel subtasks that run on distributed resources. These resources are classified into a software (SW) and a hardware (HW) domain. The software domain usually contains processors for general purpose or digital signal calculations. Dedicated co-processors such as encryption or video en-/decoding units belong to the hardware domain. Nowadays, a decision in which domain a certain subtask will be executed in a system is usually taken during system level design. This is done on the basis of certain assumptions about the system requirements that might not hold at runtime. The HW/SW partitioning is static and cannot adapt to dynamically changing system requirements at runtime. Our contribution to tackle this, is to combine a ESL based HW/SW codesign methodology with a coarse grained reconfigurable System on Chip architecture. We propose this as Preemptive HW/SW-Threading.

<p>QC 20160428</p>