In the design of a multi-processor System-on-a-Chip (SoC), the bus architecture typically comes to the forefront because the system performance is not dependent only on the speed of the Processing Elements (PEs) but also on the bus architecture in the system. An efficient bus architecture with effective arbitration for reducing contention on the bus plays an important role in maximizing performance. Therefore, among many issues of multi-processor SoC research, we focus on two issues related to the bus architecture in this dissertation. One issue is how to quickly and easily design an efficient bus architecture for an SoC. The second issue is how to quickly explore the design space across performance influencing factors to achieve a high performance bus system. The objective of this research is to provide a Computer-Aided Design (CAD) tool with which the user can quickly explore System-on-a-Chip (SoC) bus design space in search of a high performance SoC bus system. From a straightforward description of the numbers and types of Processing Elements (PEs), non-PEs, memories and buses (including, for example, the address and data bus widths of the buses and memories), our Bus Synthesis tool, called BusSynth, generates a Register-Transfer Level (RTL) Verilog Hardware Description Language (HDL) description of the specified bus system. The user can utilize this RTL Verilog in bus-accurate simulations to more quickly arrive at an efficient bus architecture for a multi-processor SoC. The methodology we propose gives designers a great benefit in fast design space exploration of bus systems across a variety of performance influencing factors such as bus types, PE types and software programming styles (e.g., pipelined parallel fashion or functional parallel fashion). We also show that BusSynth can efficiently generate bus systems in a matter of seconds as opposed to weeks of design effort to integrate together each system component by hand. Moreover, unlike the previous related work, BusSynth can support a wide variety of PEs, memory types and bus architectures (including a hybrid bus architecture) in search of a high performance SoC.

Future opportunities for gigascale integration will be governed by a hierarchy of theoretical and practical limits that can be codified as follows: fundamental, material, device, circuit, and system. An exponential increase in on-chip integration is driving System-on-Chip (SoC) methodologies as a dominant design solution for gigascale ICs. Therefore, a second generation generic systems simulator (GENESYS) is developed to address a need for rapid assessment of technology/architecture tradeoffs for multi-billion transistor SoCs while maintaining the depth of core modeling codified in the hierarchy of limits. A newly developed system methodology incorporates a hiearchical block-based model, a dual interconnect distribution for both local and global interconnects, a generic on-chip bus model, and cell placement algorithms. A comparison of simulation results for five commercial SoC implementations shows increased accuracy in predicting die size, clock frequency, and total power dissipation. ITRS projections for future technology requirments are applied with results indicating that increasing static power dissipation is a key impediment to making continued improvements in chip performance. Additionally, simulations of a generic chip multi-processor architecture utilizing several interconnect schemes shows that the most promising candidate for the future of on-chip global interconnect networks will be hierarchical bus structures providing a high degree of connectivity while maintaining high operating frequencies.

In the twenty-first century, there are still many difficulties arise on software development. For example, the growing commercial demand variability, but the software maintainable level over time becoming less and less. We have to raise the importance of software design. Using good software design approachs to face the increasingly complex commercial demand. Therefore, this study analyzed the large-scale enterprise systems for the software design problems. Based on the theory of software design, software design methodology, software architecture, design pattern and design principle, this study introduce three software design approachs:"Flexible Integration Design", "Loosely Coupled Design", and "Parameter Table Design". Using the extensibility, flexibility, pluggability and reuseability to design system integration solutions: "Unified Accounting Rule Table" and "Unified Interface". This will help the large-scale enterprise systems for software development to increase quality and efficiency.

Today, the impact of information technologies on education field is ever more clarified with the integration of new tools and methods to the education. Education has been becoming away from the traditional classroom environment through virtual environment. Besides education of theoretical disciplines, education of practice based disciplines, like design related disciplines are moving toward virtual environments. One of these is Industrial Design (ID) education which also has made the transition to the virtual world. This thesis aims to explore and scrutinize the latest forms of ID education, especially the online distance ID education. In order to comprehend the technological progress of ID education and its possible future, an overview of the origins and an evaluation of the current state of distance online ID education are made. By this study, it is expected to shed light to the design educators and the educational systems&rsquo / developers, for designing these environments. At the end of this research, it is concluded that it is not possible to imagine a future of ID education without technology integration. However, it would be better to apply both technological and traditional methods. In fact, the key people in the development of these educational systems and tools would be the designers themselves.

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Bibliography :p.269-285. / xxii, 285 p. : ill. ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Describes a new method for describing asynchronous systems (free-flow asynchronism). The method is demonstrated through two applications ; a channel signalling system and amedo. / Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1998

Bibliography: leaves 233-259 / xii, 259 leaves : ill ; 30 cm. / Title page, contents and abstract only. The complete thesis in print form is available from the University Library. / Thesis (Ph.D.)--University of Adelaide, 1991

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This thesis presents teaching fundamentals of digital logic design and VLSI design for freshmen and even for high school students using e-textiles. This easily grabs attention of students as it is creative and interesting. Using e-textiles to project these concepts would be easily understood by students at young age. This involves stitching electronic circuits on a fabric using basic components like LEDs, push buttons and so on. The functioning of these circuits is programmed in Lilypad Arduino. By using this method, students get exposed to basic electronic concepts at early stage which eventually develops interest towards engineering field.

Integrated Circuits (ICs) have a broad range of applications in healthcare, military, consumer electronics etc. The acronym VLSI stands for Very Large Scale Integration and is a process of making ICs by placing millions of transistors on a single chip. Because of advancements in VLSI design technologies, ICs are getting smaller, faster in speed and more efficient, making personal devices handy, and with more features. In this thesis work an interactive framework is designed in which the fundamental concepts of digital logic design and VLSI design such as logic gates, MOS transistors, combinational and sequential logic circuits, and memory are presented in a simple, interactive and user friendly way to create interest in students towards engineering fields, especially Electrical Engineering and Computer Engineering. Most of the concepts are explained in this framework by taking the examples which we see in our daily lives. Some of the critical design concerns such as power and performance are presented in an interactive way to make sure that students can understand these significant concepts in an easy and user friendly way.