To minimize the size of the electronic ballast, a half-bridge load- resonant inverter with a cascading Rosen-type piezoelectric transformer (PT) is designed for cold cathode fluorescent lamps (CCFLs). The electrical characteristics of the PT are investigated to obtain a higher voltage gain by adapting the load impedance to the interposed network. The circuit parameters are selected under the considerations of (1) the minimum inductor size, (2) the higher circuit efficiency, (3) the rated current of the PT, and (4) the stable lamp operation. The electronic ballasts are designed for operating the lamp at the rated lamp power and with dimming control by asymmetrical pulse-width-modulation (APWM),respectively. Laboratory circuits are assembled and, experimental tests are carried out to validate the theoretical analyse

A single-stage high-power-factor electronic ballast with class E inverter is proposed for driving the fluorescent lamp. The circuit configuration is obtained from the integration of a buck-boost converter for power-factor- correction (PFC) and a class E resonant inverter for ballasting. The integrated ballast circuit requires only one active power switch and simple control. Operating the buck-boost converter in discontinuous conduction mode (DCM) at a fixed frequency, the electronic ballast can achieve nearly unity power factor. With pulse-width-modulation (PWM), the electronic ballast can provide an appropriate filament current for preheating, a high voltage for ignition, and then a desired lamp current for steady-state operation. An additional control circuit is included to eliminate the glow current during preheating stage. The operation of the ballast-lamp circuit is analyzed by fundamental approximation. Computer simulations are made and design equations are derived on basis of the power-dependent resistance model of the fluorescent lamp. With carefully designed circuit parameters, the active power switch can be switched on at zero current to reduce the switching losses leading to a higher efficiency. An experimental circuit designed for a PL-27W compact fluorescent lamp is built and tested to verify the computer simulations and analytical predictions. Experimental results show that satisfactory performances can be obtained on the proposed electronic ballast.

This thesis proposes a single-stage high-power-factor electronic ballast with series-resonant inverter for rapid-start fluorescent lamps with zero glow current during preheating period. A buck-boost converter is integrated into the ballast as the power-factor-corrector. Two auxiliary windings are wound on the same core of the buck-boost inductor for filament heating. During the preheating period, the buck-boost converter is initiated while the series-resonant inverter is disabled by controlling the corresponding active power switches. Due to zero voltage across the lamp, the glow current can be effectively eliminated. As the filaments reach appropriate emission temperature, the series-resonant inverter is activated. The lamp is then ignited and consequently operated at the rated lamp power. Circuit analyses and experimental tests of the proposed preheating control scheme are carried out on an electronic ballast for a T8-40W rapid-start fluorescent lamp.

Distributed energy resources like solar power (PV Panels) are usually connected to the AC grid through a single phase voltage source inverter (VSI). The major drawback associated with single phase grid tie inverters is the double frequency component of the grid that appears on the DC bus link. Large electrolytic capacitors are generally employed in the inverters to eliminate the ripple component. However, their bulkiness and relatively short lifetime are motivational factors to replace them with small film capacitors. This paper presents a synchronous boost/buck based active power decoupling circuit in parallel with the dc-bus link capacitor and discusses the different types of control strategies implemented. Simulation results are presented for each control technique and it is shown that the ripple on the DC bus link is largely reduced due to inclusion of this circuit along with an expected extension of the lifetime due to the reduction in the amount of dc-bus capacitance used. / text

This report examined patent activity in two areas of the solar photovoltaic industry — inverters and mounting systems — and suggests that market creation policies contributed to innovation within these solar supply chain component areas. Relying on patent counts, the report found that patent activity for inverters and mounting systems increased substantially between 2005 and 2012. Drawing on economic research and innovation theory, the report asserts that market creation policies explain how the solar industry shifted its innovation focus toward improving downstream technology in the solar “balance of system,” creating opportunity for endogenous growth within the industry. / text

Multilevel inverters offer many well-known advantages for use in high-voltage and high-power applications, but they are also well suited for low-power applications. A single phase inverter is developed in this paper to deliver power from a residential-scale system of Photovoltaic panels to the utility grid. The single-stage inverter implements a novel control technique for the reversing voltage topology to produce a stepped output waveform. This approach increases the granularity of control over the PV systems, modularizing key components of the inverter and allowing the inverter to extract the maximum power from the systems. The adaptive controller minimizes harmonic distortion in its output and controls the level of reactive power injected to the grid. A computer model of the controller is designed and tested in the MATLAB program Simulink to assess the performance of the controller. To validate the results, the performance of the proposed inverter is compared to that of a comparable voltage-sourced inverter.

In the past, distribution systems were characterized by a unidirectional power flow where power flows from the main power generation units to consumers. However, with changes in power system regulation and increasing incentives for integrating renewable energy sources, Distributed Generation (DG) has become an important component of modern distribution systems. However, when a portion of the system is energized by one or more DG and is disconnected from the grid, this portion becomes islanded and might cause several operational and safety issues. Therefore, an accurate and fast islanding detection technique is needed to avoid these issues as per IEEE Standard 1547-2003 [1]. Islanding detection techniques are dependent on the type of the DG connected to the system and can achieve accurate results when only one type of DG is used in the system. Thus, a major challenge is to design a universal islanding technique to detect islanding accurately and in a timely manner for different DG types and multiple DG units in the system. This thesis introduces an efficient universal islanding detection method that can be applied to both Inverter-based DG and Synchronous-based DG. The proposed method relies on extracting a group of features from measurements of the voltage and frequency at the Point of Common Coupling (PCC) of the targeted island. The Random Forest (RF) classification technique is used to distinguish between islanding and non-islanding situations with the goals of achieving a zero Non-Detection Zone (NDZ), which is a region where islanding detection techniques fail to detect islanding, as well as avoiding nuisance DG tripping during non-islanding conditions. The accuracy of the proposed technique is evaluated using a cross-validation technique. The methodology of the proposed islanding detection technique is shown to have a zero NDZ, 98% accuracy, and fast response when applied to both types of DGs. Finally, four other classifiers are compared with the Random Forest classifier, and the RF technique proved to be the most efficient approach for islanding detection.

Darbe analizuojamos dažnio keitiklio į tinklą generuojamos aukštesniosios eilės harmonikos. Atlikti nagrinėjamo dažnio keitiklio tuščiosios veikos ir apkrovos bandymai, bei išmatuotos generuojamos į tinklą aukštesniosios eilės srovės harmonikos. Nustatyta netiesinių iškreipių faktoriaus priklausomybė nuo maitinimo įtampos dažnio ir apkrovos. Taip pat atliktas vieno iš tinklo taršos slopinimo įrenginių – linijinio droselio bandymas. Nustatyta, kad netiesinių iškreipių faktorius, priklausomai nuo apkrovos kito nuo 30 % iki 80 %, dirbant 50 Hz dažniu. Didinant maitinimo įtampos dažnį, netiesinių iškreipių faktorius kito nuo 43,3 % iki 79,5 %, esant nurodytąjai variklio apkrovai. Naudojant linijinį droselį, santykinis netiesinių iškreipių faktorius sumažinamas 5,8 %, dirbant 25 Hz, ir 9 %, dirbant 50 Hz maitinimo įtampos dažniu. Nustatyta, kad dažnio keitiklio į tinklą generuojamos aukštesniosios eilės srovės harmonikos gerokai viršino leistinąsias ribines vertes, atitinkamai 5-oji – 3,3 karto, 7-oji – 4,7 karto, 11-oji – 5,9 karto, 13-oji – 8,5 karto ir 15-oji – 1,8 karto. Taigi naudoti harmonikų filtrus rekomenduotina, norint užtikrinti sistemos patikimumą ir ilgesnį eksploatacijos laiką, taip pat filtrų pagalba galima apsaugoti tinklo iškraipymams jautrią įrangą. / The work analyses the higher order harmonics into power system generated by the frequency inverter. Perform issue frequency inverter non load and load test and established generates into network higher order harmonics. Established total harmonic distortion dependence of the mains frequency ant the load. Also was made research of one network pollution reduction equipment – line choke. It was found that harmonic distortion, depending on the load was varied from 30 % to 80 %, at 50 Hz operating frequency. Increasing mains voltage frequency, harmonic ranged changed from 43,3 % to 79,5 %, at full asynchronous motor load. Using line choke total demand distortion is reduced from 5,8 % at 25 Hz, to 9 % at 50 Hz mains frequency. Established that frequency inverter pollution of higher current harmonics significatly higher than allowable, accordingly, the 5 th – 3,3 time, the 7 th – 4,7 times, the 11 th – 5,9 times and the 15 th – 1,8 times. Thus, the use of harmonic filter ir recomended to ensure system reliability and longer service life, as well filter heps to protect for current distortion sensitive equipment.

This thesis presents a novel Zero Voltage Switching (ZVS) approach in a grid connected single-stage flyback inverter without using any additional auxiliary circuits. The soft-switching of the primary switch is achieved by allowing negative current from the grid-side through bidirectional switches placed on the secondary side of the transformer. Basically, the negative current discharges the MOSFET’s output capacitor thereby allowing turn-on of the primary switch under zero voltage. In order to optimize the amount of reactive current required to achieve ZVS a variable frequency control scheme is implemented over the line cycle. In addition, the bi-directional switches on the secondary side of the transformer have ZVS during the turn-on times. Therefore, the switching losses of the bi-directional switches are negligible. A 250W prototype has been implemented in order to validate the proposed scheme. Experimental results confirm the feasibility and superior performance of the converter compared to the conventional flyback inverter. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2012-07-06 16:24:13.385

In this work a low voltage and highly linear current-mode current to delay (CTD) converter is presented. The proposed current to delay converter has the improved linearity of about 23.5% when compared with a conventional–delay inverter over the input dynamic current range of 50µA. When used as front-end block in current-mode delay-mode analog to digital converter an 11-bit resolution is obtained. The design is implemented in TSMC 90 nm CMOS technology. Monte Carlo analysis and process corner analysis is performed on the proposed circuit to analyze the amount of mismatch that will degrade the performance of the circuit in a system level. A Process, Voltage, and Temperature (PVT) variation insensitive circuit is used to bias the designed CTD converter to obtain 57% reduction of variation when compared with the simple current mode biasing technique.