Superconducting Magnetic Energy Storage (SMES) has branched out from its application origins of load leveling, in the early 1970s, to include power quality for utility, industrial, commercial and military applications. It has also shown promise as a power supply for pulsed loads such as electric guns and electromagnetic aircraft launchers (EMAL) as well as for vital loads when power distribution systems are temporarily down. These new applications demand more efficient and compact high performance power electronics. A 250 kW Power Conditioning System (PCS), consisting of a voltage source converter (VSC) and bi-directional two-quadrant DC/DC converter (chopper), was developed at the Center for Power Electronics Systems (CPES) under an ONR funded program. The project was to develop advanced power electronic techniques for SMES Naval applications. This thesis focuses on system analysis and development of a demonstration test plan to illustrate the SMES systems' ability to be multitasked for implementation on naval ships. The demonstration focuses on three applications; power quality, pulsed power and vital loads. An integrated system controller, based on an Altera programmable logic device, was developed to coordinate charge/discharge transitions. The system controller integrated the chopper and VSC controller, configured applicable loads, and dictated sequencing of events during mode transitions. Initial tests with a SMES coil resulted in problems during mode transitions. These problems caused uncontrollable transients and caused protection to trigger and processors to shut down. Accurate models of both the Chopper and VSC were developed and an analysis of these mode transition transients was conducted. Solutions were proposed, simulated and implemented in hardware. Successful operation of the system was achieved and verified with both a low temperature superconductor here at CPES and a high temperature superconductor at The Naval Research Lab. / Master of Science

In a world with a growing population there is a trend toward higher and higher energy usage. Because of the cost involved in producing extra energy, there is a need for more efficient usage of the energy that is already available. The issue of efficiency rings home especially clear with electric motors. Although induction motors are used in many different applications, the motors used in electric vehicles must be able to generate a large starting torque as well as operate over a wide speed range. This work analyzes the restrictions placed on the motor and inverter drive system. It also looks at the best method for controlling the drive in order to achieve the highest efficiency out of the drive. While other works have shown methods of achieve high efficiency out of the motor, it is the assertion of this work that the efficiency of the total drive is more important. It is to that end that this work analyzes the performance of an induction motor under low torque and speed where a traction drive utilizes the most energy. / Master of Science

The wide-bandgap (WBG) devices, like gallium nitride (GaN) and silicon carbide (SiC) devices have proven to be a driving force of the development of the power conversion technology. Thanks to their distinct advantages over silicon (Si) devices including the faster switching speed and lower switching losses, WBG-based power converter can adopt a higher switching frequency and pursue higher power density and higher efficiency. As a trade-off of the advantages, there also exist the high-frequency-oriented challenges in the adoption of the GaN HEMT under research, including narrow safe gate operating area, increased switching overshoot, increased electromagnetic interference (EMI) in the gate loop and the power stages, the lack of the modules of packages for high current application, high gate oscillation under parallel operation. The dissertation is developed to addressed the all the challenges above to fully explore the potential of the GaN HEMTs. Due to the increased EMI emission in the gate loop, a small isolated capacitor in the gate driver power supply is needed to build a high-impedance barrier in the loop to protect the gate driver from interference. A 2 W dual-output gate driver power supply with ultra-low isolation capacitor for 650 V GaN-based half bridge is presented, featuring a PCB-embedded transformer substrate, achieving 85% efficiency, 1.6 pF isolation capacitor with 72 W/in3 power density. The effectiveness of the EMI reduction using the proposed power supply is demonstrated. The design consideration to build a compact 650 V GaN switching cell is presented then to address the challenges in the PCB layout and the thermal management. With the switching cell, a compact 1 kW 400 Vdc three-phase inverter is built and can operate with 500 kHz switching frequency. With the inverter, the high switching frequency effects on the inverter efficiency, volume, EMI emission and filter design are assessed to demonstrate the tradeoff of the adoption of high switching frequency in the motor drive application. In order to reduce the inverter CM EMI emission above 10 MHz, an active gate driver for 650 V GaN HEMT is proposed to control the dv/dt during turn-on and turn-off independently. With the control strategy, the penalty from the switching loss can be reduced. To build a high current power converter, paralleling devices is a normal approach. The dissertation comes up with the switching cell design using paralleled two and four 650 V GaN HEMTs with minimized and symmetric gate and power loop. The commutation between the paralleled HEMTs is analyzed, based on which the effects from the passive components on the gate oscillation are quantified. With the switching cell using paralleled GaN HEMTs, a 10 kW LLC resonant converter with the integrated litz-wire transformer is designed, achieving 97.9 % efficiency and 131 W/in3 power density. The design consideration to build the novel litz-wire transformer operated at 400 kHz switching frequency is also presented. In all, this work focuses on providing effective solutions or guidelines to adopt the 650 V GaN HEMT in the high frequency, high power density, high efficiency power conversion and demonstrates the advance of the GaN HEMTs in the hard-switched and soft-switched power converters. / Ph. D. / Silicon (Si) -based power semiconductor has developed several decades and achieved numerous outstanding performances, contributing a fast development of the power electronics. While the theatrical limit of the silicon semiconductor is almost reached limiting the progress speed to purse the high-efficiency, high-density high-reliability power conversion, the new material, including gallium-nitride (GaN) and silicon-carbide (SiC), based semiconductor, becomes the driven force to retain the development. Compared with Si-based device, GaN and SiC device own a faster switching speed and a lower on-resistance, enabling the adoption of high switching frequency and the possibility to increase the efficiency, power density and dynamic response. The GaN-based semiconductor is explored to be an even promising game changer than SiC device thanks to a higher theoretical ceiling. However, to adopt GaN-based semiconductors and fully utilize its benefits with high switching frequency, there are numerous high-frequency-oriented challenges, including high frequency oscillation at device termination, increased electromagnetic interference (EMI), the lack of the modules of packages for high current application, high frequency oscillation under parallel operation. The dissertation is developed to address the key high-frequency-oriented challenges to adopt GaN-based semiconductors in the power conversion and come up with the novel design strategy and analysis for high-switching-frequency power conversion using GaN devices. To the reduce the increased EMI emission in the gate loop, a novel PCB-embedded transformer structure is proposed to maintain a low isolation capacitor in the gate driver power supply for the GaN phase leg. With the proposed technique, the dual-output gate driver power supply can achieve high efficiency (85%), ultra-low isolation capacitor (1.6 pF) with high power density (72 W/in³ ). To reduce the high frequency oscillation at the GaN device termination, the strategy to layout GaN devices and its gate driver is proposed with corresponding thermal management. A compact structure for three-phase inverter is then presented, operating with a very high switching frequency (500 kHz). Within the inverter, the high switching frequency effects on the inverter performances are assessed to demonstrate the tradeoff and bottle neck to adopt high switching frequency in the motor drive application. In order to reduce the inverter EMI emission at high frequency ( >10 MHz), an active gate driver for GaN device is proposed for the active dv/dt control strategy. To build a high current power converter, the strategy to parallel GaN devices is proposed in the dissertation with the analysis on the commutation between the paralleled GaN devices. A high-frequency high-current litz-wire transformer structure for LLC resonant converter is presented with modeling and optimization. With the technique, a 10 kW LLC resonant converter achieves high efficiency (97.9 %) and high power density (131 W/in³).

The Class-E topology was presented as a single-switch power amplifier with high efficiency at the optimum condition, where the switch enjoys zero-voltage switching (ZVS) and zero-voltage-derivative switching (ZDS). It is also used in MHz dc-dc converters, and in inverters for wireless power transfer, induction heating, and plasma pulsing. The load current in these applications usually varies over a range. Efficiency of a conventional Class-E design degrades dramatically due to the hard switching beyond the optimum conditions. Keeping ZVS with load change in a Class-E topology is preferred within the load range. Soft switching with load variation is realized by duty cycle modulation with additional transformer, matching network, or resistance compression network. Since two ZVS requirements need to be satisfied in a conventional Class-E design, at least two parameters are tuned under load variation. Thus, changing switching frequency, duty cycle, and component values were used. Impressively, a load-independent Class-E inverter design was presented in 1990 for maintaining ZVS and output voltage under a given load change without tuning any parameters, and it was validated with experimental results recently. The operating principle of this special design (inconsistent with the conventional design) is not elucidated in the published literatures. Load-independency illucidation by a Thevenin Model – A Thevenin model is then established (although Class-E is a nonliear circuit) to explain the load-independency with fixed switching frequency and duty cycle. The input block of a Class-E inverter (Vin, Lin, Cin, and S) behaves as a fixed voltage source vth1 and a fixed capacitive impedance Xth1 in series at switching frequency. When the output block (Lo and Co) is designed to compensate Xth1, the output current phase is always equal to the phase of vth1 with resistive load (satisfies the ZVS requirement of a load-independent design). Thus, soft switching is maintained within load variation. Output voltage is equal to vth1 since Xth1 is canceled, so that the output voltage is constant regardless of output resistance. Load-independency is achieved without adding any components or tuning any parameters. Sequential design and tuning of a load-independent ZVS Class-E inverter with constant voltage based on Thevenin Model - Based on the model, it's found that each circuit parameter is linked to only one of the targeted performance (ZVS, fixed voltage gain, and load range). Thus, the sequential design equations and steps are derived and presented. In each step, the desired performance (e.g. ZVS) now could be used to check and tune component values so that ZVS and fixed voltage gain in the desired load range is guaranteed in the final Class-E inverter, even when component values vary from the expectations. The Thevenin model and the load-independent design is then extended to any duty cycles. A prototype switched at 6.78 MHz with 10-V input, 11.3-V output, and 22.5-W maximum output power was fabricated and tested to validate the theory. Soft switching is maintained with 3% output voltage variation while the output power is reduced tenfold. A load-independent ZVS Class-E inverter with constant current by combining constant voltage design and a trans-susceptance network - A load-independent ZVS Class-E inverter with constant current under load variation is then presented, by combining the presented design (generating a constant voltage) and a trans-susceptance network (transferring the voltage to current). The impact of different types and the positions of the networks are discussed, and LCL network is selected so that both constant current and soft switching are maintained within the load variation. The operation principle, design, and tuning procedures are illustrated. The trade-off between input current ripple, output current amplitude, and the working load range is discussed. The expectations were validated by a design switched at 6.78 MHz with 10-V input, 1.4-A output, and 12.6-W maximum output power. Soft switching is maintained with 16% output current varying over a 10:1 output power range. A "ZVS" Class-E dc-dc converter by adding a diode rectifier bridge and compensate the induced varying capacitance at full-load condition - The load-independent Class-E design is extended to dc-dc converter by adding a diode rectifier bridge followed by the Class-E inverter. The equivalent impedance seen by the inverter consists of a varying capacitance and a varying resistance when the output changes. As illustrated before, ZVS and constant output can only be maintained with resistive load. Since the varying capacitance cannot be compensated for the whole load range, performance with using different compensation is discussed. With the selected full-load compensation, ZVS is achieved at full load condition and slight non-ZVS occurs for the other load conditions. The expectation was validated by a dc-dc converter switched at 6.78 MHz with 11 V input, 12 V output, and 22 W maximum output power. ZVS (including slight non-ZVS) is maintained with 16% output voltage variation over 20:1 output power range. Design of variable Capacitor by connecting two voltage-sensitive capacitors in series and controlling the bias voltage of them - The equivalent varying capacitance in the Class-E dc-dc converter can be compensated in the whole load range only with variable component. The sensitivity of a Class-E power conversion can also be improved by using variable capacitors. Thus, a Voltage Controlled Capacitor (VCC) is presented, based on the intrinsic property of Class II dielectric materials that permittivity changing much with electric field. Its equivalent circuit consists of two identical Class II capacitors in series. By changing the voltage of the common point of the two capacitors (named as control voltage), the two capacitance and the total capacitance are both changed. Its operation principle, measured characteristic, and the SPICE model are illustrated. The capacitance changes from 1 μF to 0.2 μF with a control voltage from 0 V to 25 V, resulting a 440% capacitance range. Since the voltage across the two capacitors (named as output voltage) also affects one of the capacitance when control voltage is applied, the capacitance range drops to only 40% with higher bias in the output voltage. Thus, a Linear Variable Capacitor (LVC) is presented. The equivalent circuit is the same as VCC, while one of the capacitance is designed much higher to mitigate the effect of output voltage. The structure, operational principle, required specifications, design procedures, and component selection were validated by a design example, with 380% maximum capacitance range and less than 20% drop in the designed capacitor voltage range. This work contributes to • Analytical analysis and Thevenin Model in load-independent Class-E power conversion • Variable capacitance with wide range / Doctor of Philosophy / The Class-E topology was presented as a single-switch power amplifier with high efficiency at the optimum condition. Efficiency of a conventional Class-E design degrades with load variation dramatically due to the hard switching beyond the optimum conditions. Since two requirements need to be satisfied for soft switching in a conventional Class-E design, at least two parameters are tuned under load variation. Impressively, a load-independent Class-E inverter design was presented for maintaining Zero-Voltage-Switching (ZVS) and output voltage under a given load change without tuning any parameters, and it was validated with experimental results recently. A Thevenin model is established in this work to explain the realization of load-independency with fixed switching frequency and duty cycle. Based on that, a sequential design and tuning process is presented. A prototype switched at 6.78 MHz with 10-V input, 11.3-V output, and 22.5-W maximum output power was fabricated and tested to validate the theory. Soft switching is maintained with 3% output voltage variation while the output power is reduced tenfold. A load-independent ZVS Class-E inverter with constant current under load variation is then presented, by combining the presented design and a trans-susceptance network. The expectations were validated by a design switched at 6.78 MHz with 10-V input, 1.4-A output, and 12.6-W maximum output power. Soft switching is maintained with 16% output current varying over a 10:1 output power range. The load-independent Class-E design is extended to dc-dc converter by adding a diode rectifier bridge, inducing a varying capacitance. With the selected full-load compensation, ZVS is achieved at full load condition and slight non-ZVS occurs for the other load conditions. The expectation was validated by a dc-dc converter switched at 6.78 MHz with 11 V input, 12 V output, and 22 W maximum output power. ZVS (including slight non-ZVS) is maintained with 16% output voltage variation over 20:1 output power range. The varying capacitance in the Class-E dc-dc converter needs variable component to compensate. Thus, a Voltage Controlled Capacitor (VCC) is presented. The capacitance changes from 1 μF to 0.2 μF with a control voltage from 0 V to 25 V, resulting a 440% capacitance range. The capacitance range drops to only 40% with higher bias in the output voltage. Thus, a Linear Variable Capacitor (LVC) is presented, with 380% maximum capacitance range and less than 20% drop in the designed capacitor voltage range.

Traditionally, power system protection describes detecting, clearing, and locating faults in the power system. Traditional methods for detecting and locating faults may not be sufficient for inverter-based resources (IBR) as the fault response of an IBR differs from the response of a synchronous generator. As the composition of the power grid continues to evolve to integrate more IBRs that employ communication-based control algorithms; the power system is also exposed to cyberattacks. Undetected cyberattacks can disrupt normal system operation causing local outages. Therefore, power system protection must evolve with the changes in the grid to not only detect, locate, and clear faults with IBR generation but also detect and mitigate cyberattacks on IBR controllers. This thesis proposes methods for protecting an IBR-based transmission system from: (i) GPS spoofing cyberattacks on a power sharing controller; (ii) open-circuit faults. The GPS spoofing detection algorithm is a decision tree that enables either the proposed state observer--based mitigation technique or the proposed long short-term memory (LSTM)-based mitigation algorithm. The proposed logic for detecting open-circuit faults addresses each subcategory of open-circuit faults: breaker malfunctions, broken conductors, and series arc faults. PSCAD/EMTDC simulations are performed to test the effectiveness of the proposed methods. / Master of Science / The desire to reduce carbon emissions from electric power generation is resulting in the simultaneous retirement of fossil-fuel-burning electric power generation and increase in the number of renewable energy resources. These renewable energy resources, or inverter-based resources, respond differently to disturbances than traditional generators, and; therefore, require the development of new strategies to improve the disturbance response of an inverter-based resource. Disturbances in the power system can be divided into two types: (i) normal disturbances; (ii) abnormal disturbances. The response of an IBR to normal disturbances is improved with reliable control, further improved with communication, which ensures the stable operation of the power system. The abnormal conditions can also be split into two categories: (i) cyberattacks; (ii) faults. A cyberattack is when an adversary gains access a system with the goal of causing harm. In IBRs, cyberattacks can degrade power quality and lead to local outages. Faults are events that cause a change in the normal current flow in the power system. Undetected faults can cause local outages, lead to forest fires, and personnel injury; therefore, must be detected, located, can cleared in a timely manner. This work explores methods for detecting and mitigating cyberattacks and detecting faults in the presence of inverter-based resources.

The voltage source inverter (VSI) is certainly the most popular topology used in dc to ac power conversion. Virtually every commercial electric motor is driven by a VSI. There is a need for smaller and more efficient drives in high performance applications that is dictating unprecedented power density requirements on airborne motor drive systems. In reply to this need, higher switching frequencies are being sought and new switching devices like Silicon Carbide (SiC) JFETs have emerged. Although faster switching rates favor a reduction in the size of passive components and alleviate the current ripple in the inverter, a penalty is paid on switching losses. Owing to their low switching energy profile, SiC JFETs stand as promising candidates in high switching frequency environments. Their normally-on nature, however, raises a level of discomfort among designers due to the added complexities in the gate drive circuitry and the increased risk of dc bus shoot-through faults in voltage source inverters. Despite of these challenges the use of SiC JFETs continues proliferating in high power density applications. In an effort to study the new challenges introduced by this trend a 2 kW IGBT-based three-phase voltage source inverter operating at 65 kHz was designed, built, and tested. In addition a novel overcurrent protection residing in the inverter dc link is proposed in response to the concern of using normally-on devices in voltage source inverters. Successful hardware validation of both the VSI and the overcurrent protection circuit is supported with experimental results. / Master of Science

This thesis details the design and testing of a reconfigurable battery array. Reconfigurable battery arrays, specifically for mobile applications, have the potential to reduce or eliminate use of auxiliary charging, balancing, and inverter systems. Design work included a bidirectional solid state switch and a cell-to-cell bidirectional current-limiting power converter. While the overall efficiency, size, and cost of the battery pack was not competitive with existing options, it demonstrated cell-to-cell balancing and native four-level square wave AC inverter output with an array of only two cells. This demonstrates viability of the concept as well as reveals important requirements and safety features for future development of reconfigurable battery arrays.

Distributed generation for consumer applications is a relatively new field and it is difficult to satisfy both cost and performance targets. High expectations coupled with extreme cost cutting to compete with traditional technologies make converter design difficult. As power electronics mature more opportunities arise for entry into this lucrative area. An excellent understanding of converter dynamics is crucial in producing a well performing and cost competitive system. The six-switch single-phase inverter proposed in this thesis is a prime candidate for use in single households and small businesses. Its compact size and compatibility with existing electrical standards make its integration easy. However, little work is available on characterizing the system from a controls point of view. In particular balancing the two outputs with an uneven load is a concern. This thesis uses nodal and loop analysis to formulate a mathematical model of the six-switch single-phase inverter. A non-linear time invariant model is constructed for circuit simulation; details found in real circuits are added. A hardware-in-the-loop (HIL) configuration is used for more accurate simulation. In fact, its use makes for an almost seamless transition between simulation and hardware experimentation. A detailed explanation of the HIL system developed is presented. The system is simulated under various load conditions. Uneven loads and lightly loaded conditions are thoroughly examined. Controllers are verified in simulation and then are tested on real hardware using the HIL system. DC bus disturbance rejection and non-linear loads are also investigated. Acceptable inverter performance is demonstrated without expensive current sensors or high sampling frequency. / Master of Science

Exploring the integration of multi-speed gearboxes in electric vehicle (EV) drivetrains, this research presents a comprehensive analysis through detailed gearbox modelling, empirical traction machine testing, and analytical drive unit loss evaluations. The study utilizes two distinct automotive-grade electric machines – an axial-flux permanent magnet synchronous machine and an interior permanent magnet machine, the latter coupled with a single-speed gearbox – to demonstrate how multi-speed gearboxes can enhance drivetrain efficiency and performance for a subcompact EV. Extensive dynamometer testing, incorporating a variety of electrical and thermal conditions, characterizes both traction machines. Findings reveal that despite the incremental churning losses from additional gear pairs, two-speed gearboxes facilitate a more efficient operation of the electric machine, inverter, and gearbox, particularly when optimized through strategic gear ratio selection. Dynamometer testing under no-load conditions and at different temperatures underscores the impact of gearbox churning and bearing drag losses and the potential for their reduction. Detailed examinations of load-dependent and independent losses within the drive unit elucidate the interactions among drivetrain components across various gear ratios. Optimized two-speed gearboxes are shown to reduce vehicle energy consumption by up to 9% and increase driving range compared to conventional single-speed configurations, supported by strategic gear ratio selections and optimizations aimed at achieving vehicle performance targets, such as acceleration, gradeability, and top speed. This research contributes to advancing the field of electric vehicle technology by illustrating the complex trade-offs and potential enhancements achievable with multi-speed drivetrains, setting a precedent for future studies to refine gearbox performance and explore novel technologies to optimize powertrain performance across diverse operational landscapes. / Thesis / Doctor of Philosophy (PhD)

Cette thèse présente une nouvelle extension d’onduleur multiniveaux, appelé ‘Multi Neutral Point’ (MNP). Cet onduleur est déduit des topologies des structures multiniveaux ‘Neutral Point Clamped’ (NPC) et ‘Multi Point Clamped’ (MPC). Les intérêts de cette extension sont: l’absence de diodes de bouclage, la possibilité de disposer de tous les nombres de niveaux, pairs et impairs et possibilité de fonctionner en mode dégradé. Nous avons élaboré une commande rapprochée simple des transistors de puissance, d’abord pour un MNP à 3 niveaux, ensuite pour les nombres de niveaux supérieurs. Nous avons comparé les pertes de puissance d’un onduleur MNP et d’un onduleur NPC. Les pertes de l’onduleur MNP sont largement inférieures à celles de l’onduleur NPC. Dans l’optique de contrôler en courant l’onduleur MNP, une stratégie nouvelle par régulateur PID d’ordre fractionnaire est également développée. Ce contrôle permet de diminuer nettement les erreurs d’amplitude et de phase entre le courant de référence et le courant de charge. La méthode nécessite le réglage des différents paramètres de contrôle en utilisant le principe d'optimisation ‘’multi-objectif’’. Le fonctionnement de l’ensemble convertisseur-contrôle-commande est enfin largement validé par simulation et par expérimentation / This thesis presents a new extension of multilevel inverters, called 'Multi Neutral Point' (MNP). This topology is deduced from Neutral Point Clamped (NPC) and Multi Point Clamped (MPC) structures. The advantage of this extension is twofold: the absence of clamping diodes and the possibility of operating on all the numbers of levels (even and odd). We have developed a simple command; we first present the command strategy for a three levels MNP, then for a five level MNP. We have compared the power losses in the power switches of an MNP and an NPC. The power losses for an MNP are far below those of the NPC inverter. For this inverter model, we have chosen a robust current control by a fractional PID controller. This control strategy can sharply reduce the amplitude and the phase errors between the reference current and the load one. This method requires the setting of various control parameters thanks to the principle of ‘’multiobjective optimization.'' In the end the set of converter-control command is validated by simulation and experimentation; the simulated and experimental results match very well