Although scalingof CMOS technology has been predicted to continue for another decade, novel technological solutions are required to overcome the fundamental limitations of the decananometer MOS transistors. Single Electron Transistor (SET) has attracted attention mainly because of its unique Coulomb blockade oscillations characteristics, ultra low power dissipation and nanoscale feature size. Despite the high potential, due to some intrinsic limitations (e.g., very low current drive) it will be very difficult for SET to compete head-to-head with CMOS’s large-scale infrastructure, proven design methodologies, and economic predictability. Nevertheless, the characteristics of SET and MOS transistors are quite complementary. SET advocates low-power consumption and new functionality (related to the Coulomb blockade oscillations), while CMOS has advantages like high-speed driving and voltage gain that can compensate the intrinsic drawbacks of SET. Therefore, although a complete replacement of CMOS by single-electronics is unlikely in the near future, it is also true that combining SET and CMOS one can bring out new functionalities, which are unmirrored in pure CMOS technology. As the hybridization of CMOSand SET is gaining popularity, silicon SETs are appearing to be more promising than metallic SETs for their possible integration with CMOS. SETs are normally studied on the basis of the classical Orthodox Theory, where quantization of energy states in the island is completely ignored. Though this assumption greatly simplifies the physics involved, it is valid only when the SET is made of metallic island. As one cannot neglect the quantization of energy states in a semi conductive island, it is extremely important to study the effects of energy quantization on hybrid CMOSSET integrated circuits. The main objectives of this thesis are: (1) understand energy quantization effects on SET by numerical simulations; (2) develop simple analytical models that can capture the energy quantization effects; (3)analyze the effects of energy quantization on SET logic inverter, and finally; (4)developa CAD framework for CMOS-SETco-simulation and to study the effects of energy quantization on hybrid circuits using that framework. In this work the widely accepted SIMON Monte Carlo (MC) simulator for single electron devices and circuits is used to study the effects of energy quantization. So far SIMON has been used to study SETs having metallic island. In this work, for the first time, we have shown how one can use SIMON to analyze SET island properties having discrete energy states.It is shown that energy quantization mainly changes the Coulomb Blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET logic inverter. Anew model for the noise margin of SET inverter is proposed, which includes the energy quantization term. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termedas “Quantization Threshold”)that an SET inverter logic circuit can withstand before its noise margin upper bound crosses the acceptable tolerance limit. It is found that SET inverter designed with CT : CG =0.366 (where CT and CG are tunnel junction and gate capacitances respectively) offers maximum robustness against energy quantization. Then the effects of energy quantization are studied for Current biased SET (CBS), which is an integral part of almost all hybrid CMOS-SET circuits. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics though it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: Negative Differential Resistance (NDR) and Neurone Cell, which use CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term. A novel CAD framework is then developed for CMOS-SET co-simulation, whichuses MCsimulator for SET devices alongwithconventional SPICE. Using this framework, the effects of energy quantization are studied for some hybrid circuits, namely, SETMOS, multiband voltage filter, and multiple valued logic circuits. It is found that energy quantization degrades the performance of hybrid circuit, which could be compensated by properly tuning the bias current of SET devices. Though this study is primarily done by exhaustive MC simulation, effort has also been put to develop first order compact model for SET that includes energy quantization effects. Finally it has been demonstrated that the SET behavior under energy quantization can be predicted byslightlymodifyingthe existing SETcompact models that are valid for metallic devices having continuous energy states.

Induction motor (IM) drives are employed in a wide range of industries due to low maintenance, improved efficiency and low emissions. Industrial installations of high-power IM drives rated up to 30 MW have been reported. The IM drives are also employed in ultra high-speed applications with shaft speeds as high as 500; 000 rpm. Certain applications of IM drives such as gas compressors demand high power at high speeds (e.g. 10 MW at 20; 000 rpm). In high-power voltage source inverter (VSI) fed induction motor drives, the semiconductor devices experience high switching energy losses during switching transitions. Hence, the switching frequency is kept low in such high-power drives. In high-speed drives, the maximum modulation frequency is quite high. Hence, at high speeds and/or high power levels, the ratio of switching frequency to fundamental frequency (i.e. pulse number, P ) of the motor drive is quite low. Induction motor drives, operating at low-pulse numbers, have significant low-order volt-age harmonics in the output. These low-order voltage harmonics are not filtered adequately by the motor inductance, leading to high total harmonic distortion (THD) in the line current as well as low-order harmonic torques. The low-order harmonic torques may lead to severe torsional vibrations which may eventually damage the motor shaft. This thesis addresses numerous issues related to low-pulse-number operation of VSI fed IM drives. In particular, optimal pulse width modulation (PWM) schemes for minimization of line current distortion and those for minimization of a set of low-order harmonic torques are proposed for two-level and three-level inverter fed IM drives. Analytical evaluation of current ripple and torque ripple is well established for the induction motor drives operating at high pulse numbers. However, certain important assumptions made in this regard are not valid when the pulse number is low. An analytical method is proposed here for evaluation of current ripple and torque ripple in low-pulse-number induction motor drives. The current and torque harmonic spectra can also be predicted using the proposed method. The analytical predictions of the proposed method are validated through simulations and experimental results on a 3:7-kW induction motor drive, operated at low pulse numbers. The waveform symmetries, namely, half-wave symmetry (HWS), quarter-wave symmetry (QWS) and three-phase symmetry (TPS), are usually maintained in induction motor drives, operating at low switching frequencies. Lack of HWS is well known to introduce even harmonics in the line current. Impact of three-phase symmetry on line current and torque harmonic spectra is analyzed in this thesis. When the TPS is preserved, there are no triplen frequency components in the line current and also no harmonic torques other than those of order 6, 12, 18 etc. While TPS ensures that the triplen harmonics in the three-phase pole voltages are in phase, these triplen frequency harmonics form balanced sets of three-phase voltages when TPS is not preserved. Hence, triplen frequency currents flow through the stator windings. These result in torque harmonics of order 2, 4, 6, 8, 10 etc., and not just integral multiples of 6. These findings are well supported by simulation and experimental results. One can see that two types of pole voltage waveforms are possible, when all waveform symmetries (i.e. HWS, TPS and QWS) are preserved in a two-level inverter, These are termed as type-A and type-B waveforms here. Also, QWS could be relaxed, while maintain-ing HWS and TPS, leading to yet another type of pole voltage waveform. Optimal switching angles to minimize line current THD are reported for all three types of pole voltage wave-forms. Theoretical and experimental results on a 3:7-kW IM drive show that optimal type-A PWM and optimal type-B PWM are better than each other in different ranges of modulation at any given low pulse number. In terms of current THD, the optimal PWM without QWS is found to be close to the better one between optimal type-A and optimal type-B at any modulation index for a given P . A combined optimal PWM to minimize THD is proposed, which utilizes the superior one between optimal type-A and optimal type-B at any given modulation index and pulse number. The performance of combined optimal PWM is shown to be better than those of synchronous sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experiments over a wide range of speed. A frequency domain (FD) based and another synchronous reference frame (SRF) based optimal PWM techniques are proposed to minimize low-order harmonic torques. The objective here is to minimize the combined value of low-order harmonic torques of order 6, 12, 18, ..., 6(N 1), where N is the number of switching angles per quarter cycle. The FD based optimal PWM is independent of load and machine parameters while the SRF based method considers both load and machine parameters. The offline calculations are much simpler in case of FD based optimal PWM than in case of SRF based optimal PWM. The performance of the two schemes are comparable and are much superior to those of synchronous ST PWM and SHE PWM in terms of low-order harmonic torques as shown by the simulation and experimental results presented over a wide range of fundamental frequency, The proposed optimal PWM methods for two level-inverter fed motor drives to minimize the line current distortion and low-order torque harmonics, are extended to neutral point clamped (NPC) three-level inverter fed drive. The proposed optimal PWM methods for the NPC inverter are compared with ST PWM and SHE PWM, having the same number of switching angles per quarter. Simulation and experimental results on a 3:7-kW induction motor drive demonstrate the superior performance of proposed optimal PWM schemes over ST PWM and SHE PWM schemes. The di_erent optimal PWM schemes proposed for two-level and three-level inverter fed drives, having di_erent objective functions and constraints, are all analyzed from a space vector perspective. The three-phase PWM waveforms are seen as a sequence of voltage vector applied in each case. The space vector analysis leads to determination of optimal vector sequences, fast o_ine calculation of optimal switching angles and e_cient digital implementation of the proposed optimal PWM schemes. A hybrid PWM scheme is proposed for two-level inverter fed IM drive, having a maximum switching frequency of 250 Hz. The proposed hybrid PWM utilizes ST PWM at a _xed frequency of 250 Hz at low speeds. This method employs the optimal vector sequence to minimize the current THD at any speed in the medium and high speed ranges. The proposed method is shown to reduce both THD as well as machine losses signi_cantly, over a wide range of speed, compared to ST PWM Position sensorless vector control of IM drive also becomes challenging when the ratio of inverter switching frequency to maximum modulation frequency is low. An improved procedure to design current controllers, and a closed-loop ux estimator are reviewed. These are utilized to design and implement successfully a position sensorless vector controlled IM drive, modulated with asynchronous third harmonic injected (THI) PWM at a constant switching frequency of 500 Hz. Sensorless vector control is also implemented successfully, when the inverter is modulated with synchronized THI PWM and the maximum switching frequency is limited to 500 Hz.

Orientador: Carlos Alberto Canesin / Resumo: Frente aos novos desafios impostos ao cenário energético mundial, esta tese de doutorado implementa e analisa uma micro-rede de geração distribuída (GD), com acumulação e capacidade de operação conectada ou desconectada da rede de distribuição de energia elétrica (RDEE). A energia é fornecida à RDEE através de seis inversores monofásicos, constituindo uma rede trifásica, sendo três deles com capacidade de operação ilhada e conectada, e outros três com características de fonte de corrente que podem injetar energia de forma controlada, ativa ou reativa, no ponto de conexão comum (PCC). Através do sistema de acumulação com baterias do tipo chumbo-ácido, também é possível que o sistema minimize o consumo de energia da RDEE, mesmo quando não há energia solar, extraindo potência das baterias. Tendo em vista que a quase totalidade dos inversores utilizados em um sistema de GD fornecem somente potência ativa, ou trabalhem com fator de potência fixo, este trabalho também implementa o controle dinâmico de P e Q na micro-rede, atuando como compensador de tensão no PCC e promovendo melhorias na qualidade da energia elétrica. A micro-rede é gerenciada por um programa desenvolvido para o controle de todos os dispositivos essenciais presentes na GD, incluindo controle da carga e descarga do sistema de acumulação, controle dos contatores de conexão de todo o sistema, e controle do firmware dos inversores conectados, permitindo total liberdade de gestão da energia disponível, resultando numa ... (Resumo completo, clicar acesso eletrônico abaixo) / Abstract: Considering the new challenges imposed in the energetic scenario around the world, this PhD thesis implements and analyzes a micro-grid of Distributed Generation (DG) plant with accumulation and capability of operation connected or islanded from the electric power distribution grid. The system will supply power to the utility grid and local loads through six single-phase inverters, constituting a three-phase system, among which three are with capability to operate in islanded and connected mode, and the other three single-phase inverters with current source characteristic that can inject active or reactive power in a controlled manner at the point of common coupling (PCC). Through the accumulation system with lead-acid batteries technology, it is also possible that the system minimizes the utility grid consumption, though without solar energy. Given that most of the available inverters for DG are designed only to provide active power or to operate with a fixed power factor, this work, in the meantime, implements the dynamic control of the supplied active and reactive power (P and Q) in micro-grid, acting as a voltage compensator at the PCC to improve the quality of electric power. The micro-grid is managed by software designed to control and communicate with all essential devices in DG, including control of charge and discharge of the accumulation system, control of the whole system connection contactors, and the firmware control of grid connected inverters, which allow a wid... (Complete abstract click electronic access below) / Doutor

Submitted by MARCOS GUTIERREZ ALVES null (mmarkos.alves@gmail.com) on 2017-10-18T17:25:15Z No. of bitstreams: 1 Marcos Gutierrez Alves - Tese.pdf: 10359243 bytes, checksum: 24da24ccb395d0581201cc49607f4bf6 (MD5) / Approved for entry into archive by Luiz Galeffi (luizgaleffi@gmail.com) on 2017-10-23T18:18:25Z (GMT) No. of bitstreams: 1 alves_mg_dr_ilha.pdf: 10359243 bytes, checksum: 24da24ccb395d0581201cc49607f4bf6 (MD5) / Made available in DSpace on 2017-10-23T18:18:25Z (GMT). No. of bitstreams: 1 alves_mg_dr_ilha.pdf: 10359243 bytes, checksum: 24da24ccb395d0581201cc49607f4bf6 (MD5) Previous issue date: 2017-08-21 / Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) / Frente aos novos desafios impostos ao cenário energético mundial, esta tese de doutorado implementa e analisa uma micro-rede de geração distribuída (GD), com acumulação e capacidade de operação conectada ou desconectada da rede de distribuição de energia elétrica (RDEE). A energia é fornecida à RDEE através de seis inversores monofásicos, constituindo uma rede trifásica, sendo três deles com capacidade de operação ilhada e conectada, e outros três com características de fonte de corrente que podem injetar energia de forma controlada, ativa ou reativa, no ponto de conexão comum (PCC). Através do sistema de acumulação com baterias do tipo chumbo-ácido, também é possível que o sistema minimize o consumo de energia da RDEE, mesmo quando não há energia solar, extraindo potência das baterias. Tendo em vista que a quase totalidade dos inversores utilizados em um sistema de GD fornecem somente potência ativa, ou trabalhem com fator de potência fixo, este trabalho também implementa o controle dinâmico de P e Q na micro-rede, atuando como compensador de tensão no PCC e promovendo melhorias na qualidade da energia elétrica. A micro-rede é gerenciada por um programa desenvolvido para o controle de todos os dispositivos essenciais presentes na GD, incluindo controle da carga e descarga do sistema de acumulação, controle dos contatores de conexão de todo o sistema, e controle do firmware dos inversores conectados, permitindo total liberdade de gestão da energia disponível, resultando numa importante ferramenta acadêmica de aprendizagem. Adicionalmente, a planta de GD é monitorada por meio de um programa de aquisição de dados do fluxo de energia elétrica que flui entre a GD e a RDEE, armazenando os dados relevantes em um banco de dados de informações para análises em longo prazo. É apresentada uma revisão bibliográfica para o cenário energético mundial e no Brasil, além das configurações de micro-rede com GD mais utilizadas no setor atualmente. O diagrama geral da micro-rede com GD é exposto, com descrição de cada equipamento e dimensionamento das fontes de energia solar. Finalmente, resultados experimentais e estruturas dos códigos são apresentados e discutidos. / Considering the new challenges imposed in the energetic scenario around the world, this PhD thesis implements and analyzes a micro-grid of Distributed Generation (DG) plant with accumulation and capability of operation connected or islanded from the electric power distribution grid. The system will supply power to the utility grid and local loads through six single-phase inverters, constituting a three-phase system, among which three are with capability to operate in islanded and connected mode, and the other three single-phase inverters with current source characteristic that can inject active or reactive power in a controlled manner at the point of common coupling (PCC). Through the accumulation system with lead-acid batteries technology, it is also possible that the system minimizes the utility grid consumption, though without solar energy. Given that most of the available inverters for DG are designed only to provide active power or to operate with a fixed power factor, this work, in the meantime, implements the dynamic control of the supplied active and reactive power (P and Q) in micro-grid, acting as a voltage compensator at the PCC to improve the quality of electric power. The micro-grid is managed by software designed to control and communicate with all essential devices in DG, including control of charge and discharge of the accumulation system, control of the whole system connection contactors, and the firmware control of grid connected inverters, which allow a wide control over the available energy and provide a significant academic studying platform. In addition, the energy flow between the DG and the utility grid is monitored through a power quality monitoring device, which is capable to send daily reports by email. In this way, a program was developed to store and recover all the relevant data in a database for the long-term analysis, compiling the results for easy interpretation. A literature review is presented for the world energy scenario, with more focus in Brazil, besides the micro-grid configurations with DG most used in the sector currently. This work also shows the general diagram of the micro-grid with DG describing the equipment and dimensioning the solar energy sources. Finally, it demonstrates and discusses experimental results and code structures.

Cette thèse traite des convertisseurs multiniveaux destinés aux applications moteurs rapides, utilisés notamment dans le domaine de l'Oil \& Gas. L'objectif est l'étude d'une structure qui permette de réduire les pertes par commutation, en comparaison avec la topologie conventionnelle NPC (Neutral Point Clamped) 3 niveaux, actuellement utilisée. De plus, la structure de convertisseur doit permettre de fournir des grandeurs d'entrée au moteur ayant un faible taux de distorsion harmonique, de manière à ne pas créer des échauffements supplémentaires dans le moteur.Après avoir effectué une étude des différentes structures existantes, la structure NPP (Neutral Point Piloted) 3 niveaux est finalement retenue au vu de ses différentes qualités. En effet, grâce à la mise en série de composants semi-conducteurs, les pertes par commutation de ces derniers sont divisées par deux par rapport aux composants homologues de la topologie NPC. Après avoir comparé les topologies NPC et NPP en termes de forme d'onde et de répartition des pertes dans les composants, l'auteur s'intéresse à la validation expérimentale de cette structure. Les performances atteintes par le convertisseur NPP sont intéressantes puisqu'elles permettent de commuter à des fréquences deux fois plus élevées que la topologie NPC pour un courant donné ou de commuter un courant plus important pour une fréquence de commutation donnée.Les schémas de commutation des différents composants du bras NPP sont étudiés afin de comprendre le gain non négligeable obtenu sur cette structure.Malgré le fait que la structure NPP permette de commuter à des fréquences deux fois plus élevées que la structure NPC, on ne peut pas s'affranchir du filtre sinus en sortie de l'onduleur de manière à respecter les contraintes harmoniques au niveau du moteur. Ainsi, une topologie de filtre sinus à inductances couplées a été introduite / This PhD thesis deals with multilevel inverters dedicated to high speed motors applications, used in Oil \& Gas applications. The main objective is to study a topology which enables reducing switching losses, in comparison with the conventional 3-level NPC (Neutral Point Clamped) topology. Moreover, the inverter has to provide motor input signals with a low harmonic distortion level, not to create undesired additional heating in the motor. After a study of the existing topologies, the 3-level NPP (Neutral Point Piloted) topology is chosen regarding all its benefits. Indeed, thanks to series connection of semi-conductor components, switching losses can be divided by two compared to homologous components on the NPC topology. After having compared NPC and NPP topologies in terms of waveforms and losses distribution in components, the author interest is the experimental validation of this topology. The performances reached by the NPP inverter are interesting because it enables to switch two times faster than for a NPC topology for a given current or to switch a higher current for a given switching frequency. The switching schemes of the NPP leg are studied to understand the gain obtained on this topology. In spite of the fact that switching frequency can be doubled on the NPP topology, the sinus filter can not be avoided in order to respect harmonic specification on the motor. A sinus filter with coupled inductances is introduced so that to responds the different sizing criteria

The inverter dead-time is integral to the safety of a voltage source inverter (VSI). Dead-time is introduced between the complementary gating signals of the top and bottom switches in each VSI leg to prevent shoot-through fault. This thesis reports and investigates dead-time induced sub-harmonic oscillations in open-loop induction motor drives of different power levels, under light-load conditions. The thesis develops mathematical models that help understand and predict the oscillatory behaviour of such motor drives due to dead-time act. Models are also developed to study the impact of under-compensation and over-compensation of dead-time act on stability. The various models are validated through extensive simulations and experimental results. The thesis also proposes and validates active damping schemes for mitigation of such sub-harmonic oscillations. The thesis reports high-amplitude sub-harmonic oscillations in the stator current, torque and speed of a 100-kW open-loop induction motor drive in the laboratory, operating under no-load. Experimental studies, carried out on 22-kW, 11-kW, 7.5-kW and 3.7-kW open-loop induction motor drives, establish the prevalence of dead-time induced sub-harmonic oscillations in open-loop motor drives of different power levels. An experimental procedure is established for systematic study of this phenomenon in industrial drives. This procedure yields the operating region, if any, where the motor drive is oscillatory. As a first step towards understanding the oscillatory behaviour of the motor drive, a mathematical model of the VSI is derived in a synchronously revolving reference frame (SRF), incorporating the of dead-time on the inverter output voltage. This leads to a modified dynamic model of the inverter-fed induction motor in the SRF, inclusive of the dead-time act. While the rotor dynamic equations are already non-linear, dead-time is found to introduce nonlinearities in the stator dynamic equations as well. The nonlinearities in the modified dynamic model make even the steady solution non-trivial. Under steady conditions, the dead-time can be modelled as the drop across an equivalent resistance (Req0) in the stator circuit. A precise method to evaluate the equivalent resistance Req0 and a simple method to arrive at the steady solution are proposed and validated. For the purpose of stability analysis, a small-signal model of the drive is then derived by linearizing the non-linear dynamic equations of the motor drive, about a steady-state operating point. The proposed small-signal model shows that dead-time contributes to different values of equivalent resistances along the q-axis and d-axis and also to equivalent cross-coupling reactance’s that appear in series with the stator windings. Stability analysis performed using the proposed model brings out the region of oscillatory behaviour (or region of small-signal instability) of the 100-kW motor drive on the voltage versus frequency (V- f) plane, considering no-load. The oscillatory region predicted by the small-signal analysis is in good agreement with simulations and practical observations for the 100-kW motor drive. The small-signal analysis is also able to predict the region of oscillatory behaviour of an 11-kW motor drive, which is con consumed by simulations and experiments. The analysis also predicts the frequencies of sub-harmonic oscillations at different operating points quite well for both the drives. Having the validity of the small-signal analysis at different power levels, this analytical procedure is used to predict the regions of oscillatory behaviour of 2-pole, 4-pole, 6-pole and 8-pole induction motors rated 55 kW and 110 kW. The impact of dead-time on inverter output voltage has been studied widely in literature. This thesis studies the influence of dead-time on the inverter input current as well. Based on this study, the dynamic model of the inverter fed induction motor is extended to include the dc-link dynamics as well. Simulation results based on this extended model tally well with the experimentally measured dc-link voltage and stator current waveforms in the 100-kW drive. Dead-time compensation may be employed to mitigate the dead-time and oscillatory behaviour of the drive. However, accurate dead-time compensation is challenging to achieve due to various factors such as delays in gate drivers, device switching characteristics, etc. Effects of under-compensation and over-compensation of dead time are investigated in this thesis. Under-compensation is shown to result in the same kind of oscillatory behaviour as observed with dead-time, but the fundamental frequency range over which such oscillations occur is reduced. On the other hand, over-compensation of dead-time effect is shown to result in a different kind of oscillatory behaviour. These two types of oscillatory behaviour due to under- and over-compensation, respectively, are distinguished and demonstrated by analyses, simulations and experiments on the 100-kW drive. To mitigate the oscillatory behaviour of the drive, an active damping scheme is proposed. This scheme emulates the effect of an external inductor in series with the stator winding. A small-signal model is proposed for an induction motor drive with the proposed active damping scheme. Simulations and experiments on the 100-kW drive demonstrate effective mitigation of light-load instability with this active damping scheme. In the above inductance emulation scheme, the emulated inductance is seen by the sub-harmonic components, fundamental component as well as low-order harmonic components of the motor current. Since the emulated inductance is also seen by the fundamental component, there is a fundamental voltage drop across the emulated inductance, leading to reduced co-operation of the induction motor. Hence, an improved active damping scheme is proposed wherein the emulated inductance is seen only by the sub-harmonic and low-order harmonic components. This is achieved through appropriate altering in the synchronously revolving domain. The proposed improved active damping scheme is shown to mitigate the sub-harmonic oscillation effectively without any reduction in flux.

This thesis proposes control schemes and converter configurations for high power wound field synchronous motor (WFSM) drives. The model for a salient pole WFSM in any general rotating reference frame is developed which can be used to derive models along known rotor (dq) and stator flux (MT) reference frames. Based on these models, the principle of sensor-less stator flux oriented field-oriented control (FOC) for salient pole WFSM is developed. So far in the literature, control of cylindrical rotor machine only has been addressed and the effects of saliency have generally been neglected. The performance of the proposed sensor-less FOC has been demonstrated by experimentally operating a 15.8 HP salient pole WFSM using a three-level IGBT based voltage source inverter (VSI). The principle of FOC has been later extended to the control of current source load commutated inverter (LCI) fed salient pole WFSM drives, where the drawbacks present in conventional self-control method such as rigorous off-line calculation for generation of look up tables, coupling between flux and torque control etc. are eliminated. This thesis also proposes the combination of a VSI with the LCI power circuit to overcome the different disadvantages that are present in the existing LCI topology. Firstly, a novel starting scheme is proposed, where the LCI fed WFSM is started with the aid of a low power auxiliary VSI converter in a smooth manner with sinusoidal motor currents and voltages. This overcomes the difficulties of the present complex dc link current pulsing technique that has drawbacks such as pulsating torque, long starting time etc. In a second mode of operation, it is shown that the VSI can be connected to the existing LCI fed WFSM drive as a harmonic compensator in On-The-Fly mode; this will make the terminal stator current and voltage sinusoidal apart from cancellation of torque pulsations thus improving the drive performance. The above two schemes have potential as retrofit for existing drives. It is possible to combine both the advantages, mentioned above, by permanently connecting the VSI with the LCI power circuit to feed the WFSM. This proposed hybrid LCI/VSI drive can be regarded as a universal solution for high power synchronous motor drives at all power and speed ranges.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

The work addresses the design and implementation of a universal laboratory workstation designed to teach a course on electrical drives. Workplace will be formed sets consisting of DC motor with permanent magnet on a 400W power supply voltage of 24V and induction motor with 180W power on 3x24V. The engines are connected through a flexible shaft coupling. The asynchronous motor is located on the extended shaft resolver for scanning speed and rotor position. Both engines will be supplied from the transistor inverters. The workplace will be designed for maximum clearness and resistance to damage by improper handling.

This thesis deals with analysis of electric drive parts from hybrid electric vehicle, namely interior permanent magnet synchronous motor and inverter with control. First part describes a basic theory. Further, motor and inverter computer models are shown, specified simulations are performed on this models. Results are compared with values measured on real machines from accessible literary sources.