This thesis first presents a novel and highly accurate methodology for investigating the kinetics of photoacid diffusion and catalyzed-deprotection of positive-tone chemically amplified resists during post exposure bake (PEB) by in-situ monitoring the change of resist and capacitance (RC) of resist film during PEB. Deprotection converts the protecting group to volatile group, which changes the dielectric constant of resist. So the deprotection rate can be extracted from the change of capacitance. The photoacid diffusivity is extracted from the resistance change because diffusivity determines the rate of change of the acid distribution. Furthermore, by comparing the R and C curves, the dependence of acid diffusivity on reaction state can be extracted. The kinetics of non-Fickean acid transportation, deprotection, free volume generation and absorption/escaping, and resist shrinkage is analyzed and a comprehensive model is proposed that includes these chemical/physical mechanisms. Then in this thesis a novel lithographic technique, liquid immersion contact lithography (LICL) is proposed and the simulations are performed to illustrate its main features and advantages. Significant depth-of-field (DOF) enhancement can be achieved for large pitch gratings with deep-UV light (λ=248nm) illumination with both TM and TE polarizations by liquid immersion. Better than 100nm DOF can be achieved by when printing 70nm apertures. The simulation results show that it is very promising to apply this technique in scanning near field optical microscopy. Finally, a rigorous, full vector imaging model of non-ideal mask is developed and the simulation of the imaging of such a mask with 2D roughness is performed. Line edge roughness (LER) has been a major issue limiting the performance of sub-100nm photolithography. A lot of factors contribute to LER, including mask roughness, lens imperfection, resist chemistry, process variation, etc. To evaluate the effect of mask roughness on LER, a rigorous full vector model has been developed by the author. We calculate the electromagnetic (EM) field immediately after a rough mask by using TEMPEST and simulate the projected wafer image with SPLAT. The EM field and wafer image deviate from those from an ideal mask. LER is finally calculated based on the projected image.

abstract: CMOS technology is expected to enter the 10nm regime for future integrated circuits (IC). Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and process-induced variations. Intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to the continual scaling of CMOS devices. In this work the three primary intrinsic variations sources are studied, including random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF). The research is focused on the modeling and simulation of those variations and their scaling trends. Besides the three variations, a time dependent variation source, Random Telegraph Noise (RTN) is also studied. Different from the other three variations, RTN does not contribute much to the total variation amount, but aggregate the worst case of Vth variations in CMOS. In this work a TCAD based simulation study on RTN is presented, and a new SPICE based simulation method for RTN is proposed for time domain circuit analysis. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. In this work the layout dependent Vth shift due to Rapid-Thermal Annealing (RTA) are investigated. In this work, we develop joint thermal/TCAD simulation and compact modeling tools to analyze performance variability under various layout pattern densities and RTA conditions. Moreover, we propose a suite of compact models that bridge the underlying RTA process with device parameter change for efficient design optimization. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

In 1960's Gordon Moore predicted that the increase in the number of components in integrated circuits would exponentially decrease the relative manufacturing cost per component with time. The semiconductor industry has managed to keep that pace for nearly 45 years and one of the main contributors to this phenomenal improvement in technology is advancement in the field of lithography. However, the technical challenges ahead are severe and the future roadmap laid by the International Technology Roadmap for Semiconductors looks mostly red (i.e. no solution has been found to specific problem). There are efforts in the industry and academia directed toward development of newer, alternative lithographic techniques. Step and Flash Imprint Lithography (SFIL) has recently emerged as one of the most promising alternatives, capable of producing high resolution patterns. While it has numerous advantages over conventional photolithography, several engineering challenges must be overcome to eliminate defects due to the nature of contact imprinting if SFIL is to be a viable alternative technique for manufacturing tomorrow's integrated circuits. The complete filling of template features is vital in order for the SFIL imprint process to truly replicate the template features. The feature filling phenomena for SFIL was analyzed by studying diffusion of a gas, entrapped in the features, through liquid imprint resist. A simulation of the dynamics of feature filling for different pattern configurations and process conditions during the SFIL imprint step is presented. Simulations show that initial filling is pressure-controlled and very rapid; while the rest of the feature filling is diffusion-controlled, but fast enough that diffusion of entrapped gas is not a cause for non-filling of features. A theory describing pinning of an air-liquid interface at the feature edge of a template during the SFIL imprint step was developed, which shows that pinning is the main cause of non-filling of features. Pinning occurs when the pressure at the air-liquid interface reaches the pressure of the bulk liquid. At this condition, there is no pressure gradient or driving force to move the liquid and fill the feature. The effect of several parameters on pinning was examined. A SFIL process window was established and template modifications are proposed that minimize the pinning at the feature edge while still preventing any extrusion along the mesa (pattern containing area on the template) edge. Part of semiconductor manufacturing community believes that optical lithography has the capability to drive this industry further and is committed to the continuous improvement of current optical patterning approaches. Some of the major challenges with shrinking critical dimensions (CDs) in coming years are the control of line-edge roughness (LER) and other related defects. The current CDs are such that the presence or absence of even a single polymer molecule can have a considerable impact on LER. Therefore molecular level understanding of each step in the patterning process is required. Computer simulations are a cost-effective approach to explore the huge process space. Mesoscale modeling is one promising approach to simulations because it captures the stochastic phenomena at a molecular level within reasonable computational time. The modeling and simulation of the post-exposure bake (PEB) and the photoresist dissolution steps are presented. The new simulator enables efficient exploration of the statistical excursions that lead to LER and the formation of insoluble residues during the dissolution process. The relative contributions of the PEB and the dissolution step to the LER have also been examined in the low/high frequency domain. The simulations were also used to assess the commonly proposed measures to reduce LER. The goal of the work was to achieve quantification of the effect of changes in resist composition, developer concentration, and process variables on LER and the associated defectivity. / text

The microelectronics industry has made remarkable progress with the development of integrated circuit (IC) technology which depends on the advance of micro-fabrication and integration techniques. On one hand, next-generation lithography (NGL) technologies which utilize extreme ultraviolet (EUV) and the state-of-art 193 nm immmersion and double patterning lithography have emerged as the promising candidates to meet the resolution requirements of the microelectronic industry roadmap. On the other hand, the development and advanced characterization of novel resist materials with the required critical imaging properties, such as high resolution, high sensitivity, and low line edge roughness (LER), is also indispensable. In conventional multi-component chemically amplified resist (CAR) system, the inherent incompatibility between small molecule photoacid generator (PAG) and the bulky polymer resin can lead to PAG phase separation, PAG aggregation, non-uniform PAG and acid distribution, as well as uncontrolled acid migration during the post-exposure baking (PEB) processes in the resist film. These problems ultimately create the tri-lateral tradeoff between achieving the desired lithography characteristics. Novel resist materials which can relief this constraint are essential and have become one of the most challenging issues for the implementation NGL technologies. This thesis work focuses on the development and characterization of novel resist materials for NGL technologies. In the first part of the thesis work, advanced characterization techniques for studying resist fundamental properties and lithographic performance are developed and demonstrated. These techniques provide efficient and precise evaluations of PAG acid generation, acid diffusivity, and intrinsic resolution and LER of resist materials. The applicability of these techniques to the study of resist structure-function relationships are also evaluated and discussed. In the second part of the thesis work, the advanced characterization and development of a novel resist system, the polymer-bound-PAG resists, are reported. The advantages of direct incorporation of PAG functionality into the resist polymer main chain are investigated and illustrated through both experimental and modeling studies. The structure-function relationships between the fundamental properties of polymer-bound-PAG resists and their lithographic performance are also investigated. Recommendations on substantial future works for characterizing and improving resist lithographic performance are discussed at the end of this thesis work.

Many problems exist in current photoresist designs that will limit their ability to obtain the performance required for future generations of integrated circuit devices. In order to overcome these challenges, novel resist designs are required, along with advancement in the fundamental understanding of the source of these problems. A mesoscale kinetic Monte Carlo simulation of resists was developed to probe the effects of changes in resist formulation and processing. A detailed SEM simulator was developed in order to better understand the effect of metrology on the characterization of the final resist relief image. Several important structure-property relations were developed for the prediction of glass transition temperature in molecular resists and the prediction of the solubility of molecular resists in developer. Five new families of molecular resists were developed that provide solutions to some of the limitations in current resist designs. Single component molecular resists have all of the functional groups required to act as a chemically amplified resist contained in a single molecule. This eliminates inhomogeneities in the resist and provides improved line edge roughness. Non-chemically amplified molecular resists were developed that have very good sensitivity due to the unique dissolution properties of molecular resists. Negative tone molecular resists were developed that have an excellent combination of resolution, sensitivity, and line edge roughness with better resolution than has been previously seen in negative tone resists. Control methods were also developed to improve the resolution of these types of negative tone resists even further.

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. This dissertation studies five related research topics in design and manufacturing co-optimization in nanometer standard cells. First, a comprehensive sensitivity metric, which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations, is proposed. The dissertation develops first-order models to compute these sensitivities, and perform robust poly and active layout optimization by minimizing the total delay sensitivity to reduce the delay under the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners. Second, a new equivalent source/drain (S/D) contact resistance model, which accurately calculates contact resistances from contact area, contact position, and contact shape, is proposed. Based on the impact of contact resistance on the saturation current, robust S/D contact layout optimization by minimizing the lithography variation as well as by maximizing the saturation current without any leakage penalty is performed. Third, this dissertation describes the first layout decomposition methods of spacer-type self-aligned double pattering (SADP) lithography for complex 2D layouts. The favored type of SADP for complex logic interconnects is a two-mask approach using a core mask and a trim mask. This dissertation describes methods for automatically choosing and optimizing the manufacturability of base core mask patterns, generating assist core patterns, and optimizing trim mask patterns to accomplish high quality layout decomposition in SADP process. Fourth, a new cell characterization methodology, which considers a random (line-edge roughness) LER variation to estimate the device performance of a sub-45nm design, is presented. The thesis systematically analyzes the random LER by taking the impact on circuit performance due to LER variation into consideration and suggests the maximum tolerance of LER to minimize the performance degradation. Finally, this dissertation proposes a design aware LER model which claims that LER is highly related to the lithographic aerial image fidelity and the neighboring geometric proximity. With a new LER model, robust LER aware poly layout optimization to minimize the leakage power is performed. / text

The objective of this research is to demonstrate the impact of interconnect process variations, line-edge roughness and size effects on interconnect effective resistivity and ultimately chip performance. The investigation is accomplished through five tasks. In Task I, a new closed-form effective resistivity model, which is a function of line-edge roughness (LER), surface specularity and grain boundary reflectivity, is derived. In Task II, a critical path model is enhanced by including interconnect parasitics using the model in Task I. This enhancement also involves an extensive survey of foundry process data to shed light on the device resistance estimation used in the critical path model in Task II. Task III develops a Monte Carlo (MC) simulation framework called the Fast Interconnect Statistical Simulator (FISS). Using the latest International Technology Roadmap for Semiconductors (ITRS) projections, the FISS projects the impact of interconnect process variations and size effects onto high performance microprocessor units (HP-MPUs). Task IV fabricates metallic interconnect test structures with sub-100nm line-widths. The fifth task statistically calibrates the model from Task I using resistivity data measured from the test structures in Task IV.