<p>Det här examensarbetet presenterar en evaluering av en <em>Klockkorrigerare av klockpulsbredd</em>. Den består främst av en korrigerare av klockpulsbredd (<em>Duty Cycle Corrector DCC</em>) och även en fördröjningslåst loop (<em>Delayed Locked Loop </em><em>DLL</em>). Det finns många olika korrigerare av klockpulsbredden designade förut, de två populäraste arkitekturerna då har varit enkel eller dubbel återkopplings loop. Den huvudsakliga skillnaden mellan dem är att enkel återkopplings loop använder sig av en öppen loop medan den dubbla varianten istället har en stängd loop. I det här projektet kommer en ny arkitektur att presenteras. Konceptet i den nya designen är att dela upp korrigeraren av klockpulsbredden i två delar, en korrigerare och en detektor. Detektorn får utsignalen från den fördröjningslåsta loopen som insignal och talar om för korrigeraren via två utsignaler ifall signalen behöver justeras. Detektorn är uppdelad i två likadana fördröjningselement, som båda är klockade av utsignalen och dess invers från den fördröjningslåsande loopen, fast i omvänd ordning. Det här gör det möjligt att avgöra om klockpulsbredden av signalen är över eller under 50 %. Om så är fallet kommer den att justeras av korrigeraren för att sedan skickas som insignal till den fördröjningslåsande loopen.</p><p>Abstraktionsnivån för det här projektet har varit systemnivå, detta för att kunna vara riktigt säker på att arkitekturen verkligen fungerar innan ett riktigt chip tillverkas. Tips på framtida projekt är att gå vidare till schemanivå för att slutligen göra en implementering och mätningar på ett riktigt chip av den här <em>Klockkorrigeraren av klockpulsbredd </em>när det är känt att idén fungerar.</p><p> </p>

The purpose of this master thesis was to investigate how effiecient the extractionof radiofrequency quality metrics from digital video broadcast (DVB) streamscan become using software defined radio. Software defined radio (SDR) is a fairlynew technology that offers you the possibility of very flexible receivers and transmitters where it is possible to upgrade the modulation and demodulation overtime. Agama is interested in SDR for use in the Agama Analyzer, a widely deployedmonitoring probe running on top of standard services. Using SDR, Agama coulduse that in all deployments, such as DVB by cable/terrestrial/satellite (DVBC/T/S), which would simplify logistics. This thesis is an implementation of a SDR to be able to receive DVB-C. TheSDR must perform a number of adaptive algorithms in order to prevent the received symbols from being significantly different from the transmitted ones. Themain parts of the SDR include timing recovery, carrier recovery and equalization.Timing recovery performs synchronization between the transmitted and receivedsymbols and the carrier recovery performs synchronization between the carrierwave of the transmitter and the local oscillator in the receiver. The thesis discusses various methods to perform the different types of synchronizations andequalizations in order to find the most suitable methods.

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spectrum. The Digital Delta-Sigma Modulator can be directly responsible for the generation of spur because of its inherent nonlinearity and periodicity. Many deterministic and stochastic techniques associated with the architecture of the DDSM have been developed to remove the principal causes responsible for production of spurs. The nonlinearities in a frequency synthesizer are another source for the generation of spurs. In this thesis we have predicted that specific nonlinearities in a fractional-N frequency synthesizer produce spurs at well-defined frequencies even if the output of the DDSM is spur-free. Different spur free DDSM architectures have been investigated for the analysis of spurious tones in the output spectrum of fractional-N frequencysynthesizers. The thesis presents simulation and experimental investigation of mechanisms for spur generation in a fractional-N frequency synthesizer. Simulations are carried out using the CppSim system simulator, MATLAB and Simulink while the experiments are performed on an Analog Devices ADF7021, a high performance narrow-band transceiver IC.

La tesi estudia el problema de la síntesi de freqüències en les bandes de freqüències de microones i ones mil·limètriques, i la seva aplicació al disseny dels oscil·ladors locals d'un receptor coherent per a la recepció de les *radiobalises que a 12, 20 i 30 GHz emetia el satèl·lit Olympus de l'Agència Espacial Europea (ESA), amb la finalitat de caracteritzar el comportament radioelèctric de l'atmosfera a aquestes freqüències, a partir de mesures d'atenuació i transpolarització sobre aquests senyals de test, tot això dintre del marc d'un experiment de propagació (OPEX) propiciat per l'agència.La tesi s'ha centrat en l'estudi dels sistemes de síntesis de freqüències utilitzats habitualment, i especialment en els de síntesi indirecta de freqüència basats en sistemes Phase Locked Loop (PLL) a freqüències de microones ja que són la base sobre la qual s'han dissenyat i construït els prototips de multiplicadors de freqüència que s'han desenvolupat, capaços de sintetitzar senyals en bandes de mil·limètriques, que en el nostre cas s'han restringit al marge de 1 a 29 GHz.Alguns dels multiplicadors fan ús de la detecció de fase harmònica, sistema que permet realitzar multiplicacions de freqüència d'índex imparell, evitant la utilització de divisors de freqüència en el llaç de realimentació del PLL.La tesi s'estructura en quatre parts diferenciades. La primera, amb un caire eminentment teòric, s'ofereix a manera de revisió dels aspectes del soroll de fase i dels sistemes de síntesis de freqüències existents. La segona part aborda les qüestions derivades de la síntesi de freqüències en microones mitjançant PLL's, amb descripció dels components utilitzats, per a passar a tractar dels aspectes de disseny d'un receptor coherent, els seus requisits i aplicacions. En la tercera part es presenten els multiplicadors de freqüència realitzats, la seva descripció, esquema de blocs i resultats experimentals obtinguts. I finalment, en la quarta part s'inclouen una sèrie de realitzacions derivades de la utilització de sistemes PLL a freqüències de microones, amb sincronització per injecció del VCO al senyal de referència, en aplicacions de combinació de potència i de control electrònic de fase en sistemes phased-arrays amb elements actius. / La tesis estudia el problema de la síntesis de frecuencias en las bandas de frecuencias de microondas y ondas milimétricas, y su aplicación al diseño de los osciladores locales de un receptor coherente para la recepción de las radiobalizas que a 12, 20 y 30 GHz emitía el satélite Olympus de la Agencia Espacial Europea (ESA), con la finalidad de caracterizar el comportamiento radioeléctrico de la atmósfera a estas frecuencias, a partir de medidas de atenuación y transpolarización sobre esas señales de test, todo ello dentro del marco de un experimento de propagación (OPEX) propiciado por la agencia.La tesis se ha centrado en el estudio de los sistemas de síntesis de frecuencias utilizados habitualmente, y en especial en los de síntesis indirecta de frecuencia basados en sistemas Phase Locked Loop (PLL) a frecuencias de microondas puesto que son la base sobre la que se sustentan los prototipos de multiplicadores de frecuencia que se han desarrollado, capaces de sintetizar señales en bandas milimétricas, que en nuestro caso se han restringido al margen de 1 a 29 GHz.Algunos de los multiplicadores hacen uso de la detección de fase armónica, sistema que permite realizar multiplicaciones de frecuencia de índice impar, evitando el empleo de divisores de frecuencia en el lazo de realimentación del PLL.La tesis se estructura en cuatro partes diferenciadas. La primera, con un cariz eminentemente teórico, se ofrece a modo de revisión del tema del ruido de fase y de los sistemas de síntesis de frecuencias existentes. La segunda parte aborda las cuestiones derivadas de la síntesis de frecuencias en microondas mediante PLL's, con descripción de los componentes utilizados, para pasar a tratar de los aspectos de diseño de un receptor coherente, sus requisitos y aplicaciones. En la tercera parte se presentan los multiplicadores de frecuencia realizados, su descripción, esquema de bloques y resultados experimentales obtenidos. Y por último, en la cuarta parte se incluyen una serie de realizaciones derivadas de la utilización de sistemas PLL a frecuencias de microondas, con sincronización por inyección del VCO a la señal de referencia, en aplicaciones de combinación de potencia y de control electrónico de fase en sistemas phased-arrays con elementos activos. / The thesis studies the problem of the synthesis of frequencies in the microwave and millimeter waves frequency bands, and its application to the design of the local oscillators of a coherent receiver for the reception of the radio beacons that to 12, 20 and 30 GHz emitted the satellite Olympus from the European Space Agency (ESA), with the aim of characterizing the radio behavior of the atmosphere at these frequencies, from measurements of attenuation and transpolarisation on those signals of test, all that in the framework of a propagation experiment (OPEX) favored by the agency.The thesis has been focused on the study of the frequency synthesis systems, and especially on the indirect frequency synthesis systems based on Phase Locked Loops (PLL) at microwave frequencies, since they are the base on which the prototypes of frequency multipliers that they have been developed, capable of synthesizing signals in millimeter bands, are held that in our case they have restricted regardless of 1 to 29 GHz.Some of the multipliers make use of the harmonic phase detection system that allows carrying out frequency multiplications of odd index, preventing the use of frequency dividers in the feedback loop of the PLL.The thesis is structured in four differentiated parts. The first, with an eminently theoretical look, offers like revision of the subject of the phase noise and the methods of frequency synthesis. The second part tackles the questions derived from the synthesis of frequencies in microwaves through PLL's, with description of the used components, to pass to deal of the aspects of design of a coherent receiver, its requirements and applications. In the third part the frequency multipliers carried out, its description, schema of blocks and obtained experimental results are presented. And finally, in the fourth part a series of accomplishments are included phased-arrays derived of the use of systems PLL at frequencies of microwaves, with synchronization by injection of the VCO to the reference signal, in applications of power combination and of electronic phase control in systems with active elements.

Det här examensarbetet presenterar en evaluering av en Klockkorrigerare av klockpulsbredd. Den består främst av en korrigerare av klockpulsbredd (Duty Cycle Corrector DCC) och även en fördröjningslåst loop (Delayed Locked Loop DLL). Det finns många olika korrigerare av klockpulsbredden designade förut, de två populäraste arkitekturerna då har varit enkel eller dubbel återkopplings loop. Den huvudsakliga skillnaden mellan dem är att enkel återkopplings loop använder sig av en öppen loop medan den dubbla varianten istället har en stängd loop. I det här projektet kommer en ny arkitektur att presenteras. Konceptet i den nya designen är att dela upp korrigeraren av klockpulsbredden i två delar, en korrigerare och en detektor. Detektorn får utsignalen från den fördröjningslåsta loopen som insignal och talar om för korrigeraren via två utsignaler ifall signalen behöver justeras. Detektorn är uppdelad i två likadana fördröjningselement, som båda är klockade av utsignalen och dess invers från den fördröjningslåsande loopen, fast i omvänd ordning. Det här gör det möjligt att avgöra om klockpulsbredden av signalen är över eller under 50 %. Om så är fallet kommer den att justeras av korrigeraren för att sedan skickas som insignal till den fördröjningslåsande loopen. Abstraktionsnivån för det här projektet har varit systemnivå, detta för att kunna vara riktigt säker på att arkitekturen verkligen fungerar innan ett riktigt chip tillverkas. Tips på framtida projekt är att gå vidare till schemanivå för att slutligen göra en implementering och mätningar på ett riktigt chip av den här Klockkorrigeraren av klockpulsbredd när det är känt att idén fungerar.

This thesis puts focus on the technological challenges for Wavelength Division Multiplexed Passive Optical Network (WDM-PON) implementation, and presents novel semiconductor optical devices for deployment at the optical network unit (ONU). The first-ever reported L-band Reflective semiconductor optical amplifier (RSOA) is presented based on InP-base material. A theoretical model is developed to estimate the optical gain and the saturation power of this device compared to a conventional SOA. Experiments on this device design show long-range telecom wavelength operation, with polarization-independent gain of greater than 20 dB, and low saturation output power of 0 dBm suitable for PON applications. Next, the effect of the amplified spontaneous emission noise of RSOA devices on WDM-PON system is investigated. It is shown through theoretical modeling and simulations that the RSOA noise combined with receiver noise statistics increase probability of error, and induce considerable power penalties to the WDM-PON system. By improving the coupling efficiencies, and by distributing more current flow to the input of these devices, steps can be taken to improve device noise characteristics. Further, in spectrally-spliced WDM-PONs deploying RSOAs, the effect of AWG filter shape on system performance is investigated. Simulation modeling and experiments show that deployment of Flat-band AWGs is critical for reducing the probability of error caused by AWG spectral shape filtering. Flat-band athermal AWGs in comparison to Gaussin-shape counterparts satisfy the maximum acceptable error probability requirements, and reduce the power penalty associated with filtering effect. In addition, detuning between two AWG center wavelengths impose further power penalties to the WDM-PON system. In the last section of this thesis, motivated by RSOA device system limitations, a novel injection-locked Fabry-Perot (IL-FP) device is presented which consists of a gain section monolithically integrated with a phase section. The gain section provides locking of one FP mode to a seed source wavelength, while the phase modulator allows for adjusting the wavelength of the internal modes by tuning bias current to maintain mode-locking. This device counters any mode drifts caused by temperature variations, and allows for cooler-less operation over a wide range of currents. The devices and the performance metrics subsequently allow for a hybrid integration platform on a silicon substrate and integrate many functionalities like reflective modulator with thin film dielectric filter and receiver on a single chip for deployment at the user-end of future-proof low cost WDM-PONs.

Digital communication systems invariably employ an underlying analog communication channel. At the transmitter, data is modulated to obtain an analog waveform which is input to the channel. At the receiver, the output of the channel needs to be mapped back into the discrete domain. To this effect, the continuous-time received waveform is sampled at instants chosen by the timing recovery block. Therefore, timing recovery is an essential component of digital communication systems. A widely used timing recovery method is based on a phase-locked loop (PLL), which updates its timing estimates based on a decision-directed device. Timing recovery performance is a strong function of the reliability of decisions, and hence, of the channel signal-to-noise ratio (SNR). Iteratively decodable error-control codes (ECCs) like turbo codes and LDPC codes allow operation at SNRs lower than ever before, thus exacerbating timing recovery. We propose iterative timing recovery, where the timing recovery block, the equalizer and the ECC decoder exchange information, giving the timing recovery block access to decisions that are much more reliable than the instantaneous ones. This provides significant SNR gains at a marginal complexity penalty over a conventional turbo equalizer where the equalizer and the ECC decoder exchange information. We also derive the Cramer-Rao bound, which is a lower bound on the estimation error variance of any timing estimator, and propose timing recovery methods that outperform the conventional PLL and achieve the Cramer-Rao bound in some cases. At low SNR, timing recovery suffers from cycle slips, where the receiver drops or adds one or more symbols, and consequently, almost always the ECC decoder fails to decode. Iterative timing recovery has the ability to corrects cycle slips. To reduce the number of iterations, we propose cycle slip detection and correction methods. With iterative timing recovery, the PLL with cycle slip detection and correction recovers most of the SNR loss of the conventional receiver that separates timing recovery and turbo equalization.

Frequency synthesizer is a key building block of fully-integrated wireless communication systems. Design of a frequency synthesizer requires the understanding of not only the circuit-level but also of the transceiver system-level considerations. This dissertation presents a full cycle of the synthesizer design procedure starting from the interpretation of standards to the testing and measurement results. A new methodology of interpreting communication standards into low level circuit specifications is developed to clarify how the requirements are calculated. A detailed procedure to determine important design variables is presented incorporating the fundamental theory and non-ideal effects such as phase noise and reference spurs. The design procedure can be easily adopted for different applications. A BiCMOS frequency synthesizer compliant for both wireless local area network (WLAN) 802.11a and 802.11b standards is presented as a design example. The two standards are carefully studied according to the proposed standard interpretation method. In order to satisfy stringent requirements due to the multi-standard architecture, an improved adaptive dual-loop phase-locked loop (PLL) architecture is proposed. The proposed improvements include a new loop filter topology with an active capacitance multiplier and a tunable dead zone circuit. These improvements are crucial for monolithic integration of the synthesizer with no off-chip components. The proposed architecture extends the operation limit of conventional integerN type synthesizers by providing better reference spur rejection and settling time performance while making it more suitable for monolithic integration. It opens a new possibility of using an integer-N architecture for various other communication standards, while maintaining the benefit of the integer-N architecture; an optimal performance in area and power consumption.

The object of this research is to develop robust wire-line systems which demonstrate high performance while simultaneously consuming low power. The main focus of this work is the Clock and Data Recovery (CDR) system, which is the primary circuit of any modern wire-line transceiver. Different techniques starting from circuit-level to system-level have been investigated in this work to improve the performance of multi-gigabit CDRs. A 62 GHz bandwidth amplifier has been presented to address the need for a scalable amplifier for CDR needs. A new technique has been proposed to improve the radiation immunity of latches, to reduce the BER in CDRs occurring due to package radiations. An injection-lock based clock recovery method was investigated as an alternative to PLL based CDRs as they can be used for burst-mode wire-line communication. The investigation yielded the vulnerability of the method to jitter (false-locking and high jitter transfer), the attenuation of which is critical to commercial CDRs. A novel false-lock detector system has been proposed and demonstrated for the first time as a robust solution to the issue of false-locking of CDRs due to repetitive patterns. The implementation of the final CDR system required the use of an L-C tank VCO, the components of which are generic for all commercial CDRs. A new systematic layout technique for the VCO has been proposed and demonstrated in this work to substantially improve the layout area and the associated parasitics, approximately by 70 %. This new layout addresses a critical yet often neglected part of VCO design. Furthermore, a new concept has been proposed to optimize static dividers with respect to their power consumption and number of devices.

A frequency synthesizer plays a critical role in defining the performance of wireless systems in terms of measures such as operating frequency range, settling time, phase noise and spur performance, and area/power consumption. As the trend in mobile system design has changed from single-standard systems to multi-standard/multi-application systems, the role of frequency synthesizers has become even more important. As the most popular architecture, a phase-locked loop (PLL)-based frequency synthesizer has been researched over the last several decades; however, many unsolved problems related to the PLL-based synthesizer are still waiting for answers. This dissertation addresses key challenges related to fully integrated PLL-based frequency synthesizers, including the problem of large area consumption of passive components, the inherent reference-spur problem, and the problem of trade-offs between integer-N PLLs and fractional-N PLLs. In this dissertation, new techniques and architectures are presented and developed to address those challenges. First, a low-phase-noise ring oscillator and a capacitor multiplier with a high-multiplication factor efficiently minimize the silicon area of sub-components, and a compact programmable delay-locked loop (DLL)-based frequency multiplier is developed to replace the PLL-based frequency synthesizer. Second, the charge-distribution mechanism for suppressing reference spurs is theoretically analyzed, and an edge interpolation technique for implementing the mechanism is developed. Finally, the concept and the architecture of sub-integer-N PLL is proposed and implemented to remove trade-offs between conventional integer-N PLLs and fractional-N PLLs.