1 |
Primitive interval labelled net model for logic simulation /Chiu, Ping-kuen, Peter. January 1991 (has links)
Thesis (Ph. D.)--University of Hong Kong, 1992.
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2 |
High performance and energy efficient adder design /Sun, Sheng, January 2006 (has links)
Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 132-136).
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3 |
Double barrier resonant tunnelling diodes and applicationsSellai, Azzouz January 1991 (has links)
No description available.
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4 |
Detecting bridging faults in CMOS circuitsEvans, Richard J. January 1991 (has links)
No description available.
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5 |
Decomposition and simplification with EXOR-based representationsMetzgen, Paul January 1999 (has links)
No description available.
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6 |
Algorithms for the design of VLSI floorplans and logic modules /Young, Fung Yu, January 1999 (has links)
Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 122-130). Available also in a digital version from Dissertation Abstracts.
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7 |
A tunnel diode logic network with artibrary fan-in and fan-out capabilityBell, Lynn Stephen, 1938- January 1964 (has links)
No description available.
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8 |
The automatic test pattern generation in the logic gate level circuits and MOS transistor circuits at Ohio UniversityLee, Hoon-Kyeu. January 1986 (has links)
Thesis (M.S.)--Ohio University, November, 1986. / Title from PDF t.p.
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9 |
CMOS gate delay, power measurements and characterization with logical effort and logical powerWunderlich, Richard Bryan. January 2009 (has links)
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Paul Hasler; Committee Member: David V Anderson; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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10 |
Self-calibrating differential output prediction logic /Chong, Kian Haur. January 2006 (has links)
Thesis (Ph. D.)--University of Washington, 2006. / Vita. Includes bibliographical references (leaves 90-92).
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