This dissertation presents the modeling, design, fabrication, and experimental testing of a polyimide based micro mirror for applications in MEMS logic devices based on its static behavior and in MEMS resonators using mixed frequency excitation. First, a universal MEMS logic device that can perform all the logic operations, such as INVERTER, AND, NAND, NOR, and OR gates using one physical structure, within an operating range of 0-10 volts. It can also perform XOR and XNOR with one access inverter using the same structure with different electrical interconnects. We discuss the fabrication, simulations and experimental results demonstrating these logic operations on a polyimide micro mirror. The device is capable of performing the switching operation with a frequency of 1 kHz, a switching time of 8.2 μs, and an electrical lifetime of 8000 cycles. Second, this study presents an experimental and theoretical investigation of a micro mirror under a mixed frequency signal composed of two harmonic AC sources. The experimental and theoretical dynamics are explored via frequency sweeps in the desired neighborhoods. One frequency is fixed while the other frequency is swept through a wide 5 range to study the dynamic responses of the micro mirror. These responses are studied under different frequencies and different input voltages. The results show interesting dynamics, where the system exhibits primary resonance, and combination resonances of additive and subtractive type. The mixed excitation is demonstrated as a way to increase the bandwidth of the resonator near primary resonance, which can be promising for resonant sensing applications in the effort to increase the signal-noise ratio over extended frequency range. It can be promising for energy harvesting as well; since it provides the system with resonances of very high amplitudes at very low frequencies regardless of what is the natural frequency of the system, however this still needs further investigation.

Avec les réductions d'échelle, les circuits électroniques deviennent de plus en plus petits, plus performants, consommant moins de puissance, mais aussi moins fiables. En effet, la fiabilité s'est récemment érigée en défi majeur dans l'industrie micro-électronique, devenant un critère de conception important, au même titre que la surface, la consommation de puissance et la vitesse. Par exemple, les défauts physiques dus aux imperfections dans le procédé de fabrication ont été observés plus fréquemment, affectant ainsi le rendement des circuits. Par ailleurs, les circuits nano-métriques deviennent pendant leur durée de vie plus vulnérables aux rayonnements ionisants, ce qui cause des fautes transitoires. Les défauts de fabrication, aussi bien que les fautes transitoires, diminuent la fiabilité des circuits intégrés. En avançant dans les nœuds technologiques, les circuits logiques programmables de type FPGA sont les premiers à entrer sur le marché, grâce à leur faible coût de développement et leur flexibilité qui leur permet d'être utilisés pour n'importe quelle application. Les FPGA possèdent des caractéristiques attrayantes, notamment pour les applications spatiales et aéronautiques, où la reconfigurabilité, les hautes performances et la faible consommation de puissance peuvent être exploitées pour développer des systèmes innovants. Néanmoins, les missions ont lieu dans un environnement rude, riche en radiations pouvant produire des erreurs soft dans les circuits électroniques. Ceci montre l'importance de la fiabilité des FPGA en tant que critère de conception dans les applications critiques. La plupart des FPGA commerciaux ont une architecture matricielle et leurs blocs logiques sont regroupés en clusters. Ainsi, cette thèse s'intéresse à la tolérance aux fautes des blocs de base ( blocs logiques élémentaires (BLE) et boîtes d'interconnexion ) dans un FPGA de type « matrice de clusters ». Dans le but d'améliorer la fiabilité de ces blocs, il est impératif de pouvoir d'abord l'évaluer, pour ensuite sélectionner la bonne technique de durcissement selon le budget mis à disposition. C'est bien le plan principal de cette thèse. Elle a essentiellement deux objectifs : (a) analyser la tolérance aux fautes des blocs de base dans un FPGA de type « matrice de clusters », et identifier les composants les plus vulnérables. (b) proposer des méthodes de durcissement à différents niveaux de granularité, en fonction du budget de durcissement. En ce qui concerne le premier objectif, une méthodologie pour évaluer la fiabilité du cluster a été proposée. Cette méthodologie emploie une méthode analytique déjà existante pour évaluer la fiabilité des circuits logiques combinatoires. La même méthode est utilisée pour identifier les blocs les plus éligibles au durcissement. Quant au deuxième objectif, des techniques de durcissement ont été proposées aux niveaux multiplexeur et transistor. Au niveau multiplexeur, deux solutions de durcissement ont été présentées. La première solution a recours à la redondance spatiale et concerne la structure du bloc logique. Une nouvelle architecture de BLE baptisée « Butterfly » est introduite. Elle a été comparée avec d'autres architectures de BLE en termes de fiabilité et de surcoût. La deuxième solution de durcissement est une technique dite « sans redondance ». Elle est basée sur une synthèse intelligente qui consiste à chercher la structure la plus fiable parmi toutes celles proposées dans la librairie du fondeur, avant d'utiliser directement de la redondance. Ensuite, au niveau transistor, de nouvelles architectures de multiplexeur, à sortie unique ou différentielles, ont été proposées. Elles ont été comparées à d'autres assemblages différents de transistors, selon des métriques de conception appropriées. / As feature sizes scale down to nano-design level, electronic devices have become smaller, more performant, less power-onsuming, but also less reliable. Indeed, reliability has arisen as a serious challenge in nowadays’ microelectronics industry and as an important design criterion, along with area, performance and power consumption. For instance, physical defects due to imperfections in the manufacturing process have been observed more frequently, impacting the yield. Besides, nanometric circuits have become more vulnerable during their lifetime to ionizing radiation which causes transient faults. Both manufacturing defects and transient faults contribute to decreasing reliability of integrated circuits. When moving to a new technology node, Field Programmable Gate Arrays (FPGAs) are the first coming into the market, thanks to their low development and Non-Recurring Engineering (NRE) costs and their flexibility to be used for any application. FPGAs have especially attractive characteristics for space and avionic applications, where reconfigurability, high performance and low-power consumption can be fruitfully used to develop innovative systems. However, missions take place in a harsh environment, rich in radiation, which can induce soft errors within electronic devices. This shows the importance of FPGA reliability as a design criterion in safety and critical applications. Most of commercial FPGAs have a mesh architecture and their logic blocks are gathered into clusters. Therefore, this thesis deals with the fault tolerance of basic blocks (clusters and switch boxes) in a mesh of clusters FPGA. These blocks are mainly made up of multiplexers. In order to improve their reliability, it is imperative to be able to assess it first, then select the proper hardening approach according to the available budget. So, this is the main outline in which this thesis is conceived. Its goals are twofold: (a) analyze the fault tolerance of the basic blocks in a mesh of clusters FPGA, and point out the most vulnerable components (b) propose hardening schemes at different granularity levels, depending on the hardening budget. As far as the first goal is concerned, a methodology to evaluate the reliability of the cluster is proposed. This methodology uses an existent analytical method for reliability computation of combinational circuits. The same method is employed to identify the worthiest components to be hardened. Regarding the second goal, hardening techniques are proposed at both multiplexer and transistor levels. At multiplexer level, two hardening solutions are presented. The first solution resorts to spacial redundancy and concerns the logic block structure. A novel Configurable Logic Block (CLB) architecture baptized Butterfly is introduced. It is compared with other hardened CLB architectures in terms of reliability and cost penalties. The second hardening solution is a redundanceless scheme. It is based on a “smart” synthesis that consists in seeking the most reliable design in a given founder library, instead of directly using a redundant solution. Then, at transistor level, new single-ended and dual-rail multiplexer architectures are proposed. They are compared to different other transistor structures, according to suitable design metrics.

Magnetic nanoscale devices have shown great promise in both research and industry. Magnetic nanostructures have potential for non-volatile data storage applications, reconfigurable logic devices, biomedical devices and many more. The S-state magnetic element is one of the promising structures for non-volatile data storage applications and reconfigurable logic devices. It is a single-layer logic element that can be integrated in magnetoresistive structures. We present a detailed micromagnetic analysis of the geometrical parameter space in which the logic operation is carried out. The influence of imperfections, such as sidewall roughness and roundness of the edge is investigated. Magnetic nanowires are highly attractive materials that has potential for applications in ultrahigh magnetic recording, logic operation devices, and micromagnetic and spintronic sensors. To utilize applications, manipulation and assembly of nanowires into ordered structures is needed. Magnetic self-alignment is a facile technique for assembling nanowires into hierarchical structures. In my thesis, I focus on synthesizing and assembling nickel nanowires. The magnetic behaviour of a single nickel nanowire with 200~nm diameter is investigated in micromagnetic simulations. Nickel nanowires with Au caps at the ends were synthesized by electrochemical deposition into nanopores in alumina templates. One-dimensional alignment, which forms chains and two-dimensional alignment, which forms T-junctions as well as cross-junctions are demonstrated. Attempts to achieve three-dimensional alignment were not successful yet. I will discuss strategies to improve the alignment process.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第18990号 / 工博第4032号 / 新制||工||1621 / 31941 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 北野 正雄, 准教授 山田 啓文 / 学位規則第4条第1項該当

The analysis of logic device characterization have been performed. Logic device sorts and its characterization analysis was made. The analysis of other logic device test system was performed. The logic test system requirements was made. The hardware project of logic device test system and system hardware mounting was made. The software for the logic device test system was made. Experimentation of logic device test system was performed. The results of experimentation was given. Graphs about logic test system analysis of trustiness research was given. Performed finding about the logic device test system accordance for technical requirements, trustiness and universality.

Magnetic nanoscale devices have shown great promise in both research and industry. Magnetic nanostructures have potential for non-volatile data storage applications, reconfigurable logic devices, biomedical devices and many more. The S-state magnetic element is one of the promising structures for non-volatile data storage applications and reconfigurable logic devices. It is a single-layer logic element that can be integrated in magnetoresistive structures. We present a detailed micromagnetic analysis of the geometrical parameter space in which the logic operation is carried out. The influence of imperfections, such as sidewall roughness and roundness of the edge is investigated. Magnetic nanowires are highly attractive materials that has potential for applications in ultrahigh magnetic recording, logic operation devices, and micromagnetic and spintronic sensors. To utilize applications, manipulation and assembly of nanowires into ordered structures is needed. Magnetic self-alignment is a facile technique for assembling nanowires into hierarchical structures. In my thesis, I focus on synthesizing and assembling nickel nanowires. The magnetic behaviour of a single nickel nanowire with 200~nm diameter is investigated in micromagnetic simulations. Nickel nanowires with Au caps at the ends were synthesized by electrochemical deposition into nanopores in alumina templates. One-dimensional alignment, which forms chains and two-dimensional alignment, which forms T-junctions as well as cross-junctions are demonstrated. Attempts to achieve three-dimensional alignment were not successful yet. I will discuss strategies to improve the alignment process.

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第18990号 / 工博第4032号 / 新制||工||1621(附属図書館) / 31941 / 京都大学大学院工学研究科電気工学専攻 / (主査)教授 引原 隆士, 教授 北野 正雄, 准教授 山田 啓文 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Approved for public release, distribution is unlimited / This thesis outlines the development, programming, and testing a logical interface between a radar system, the AN/SPS-65(V)1, and a general-purpose reconfigurable computing platform, the SRC Computer, Inc. model, the SRC-6E. To confirm the proper operation of the interface and associated subcomponents, software was developed to perform basic radar signal processing. The interface, as proven by the signal processing results, accurately reflects radar imagery generated by the radar system when compared to maps of the surrounding area. The research accomplished here will allow follow on research to evaluate the potential benefits reconfigurable computing platforms offer for radar signal processing. / Captain, United States Marine Corps

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / The Precision Fires Rocket and Missile Systems (PFRMS) Program Office continually undertakes Stockpile Reliability Testing (SRP) to ensure the validity of the accumulated weapons and increase the she lf life of these weapon systems. MLRS is a legacy weapon system that has been undergoing SRP testing for over 20 years. The PFRMS Program Office has a need for a miniature Tactical Telemetry System that will monitor the fuze performance of the MLRS Rocket during SRP testing. This paper will address a technical approach of how a small Tactical Telemetry System could be built to meet this requirement. The Tactical Telemetry system proposed in this paper will monitor fuze functions, operate across the wide environmental spectrum of the SRP tests, and physically fit in the nose area without altering the overall tactical rocket appearance or operation.

Si complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices. / text