As the complexity of System-on-a-Chip (SoC) designs increases, embedded memory components gradually occupy a significant portion of the total area cost, and the reusable memory Intellectual Property (IP) design becomes a critical issue. In this thesis, an automatic cache generator is developed which can be easily integrated into the current cell-based design flow. The generated cache contains both hard IP and soft IP. The storage array circuits are implemented as hard IP to reduce the area cost. The cache control unit is realized as soft IP. The hard IP of the core memory circuits mainly store data and tag information. The implementations of tag arrays can be divided into two categories: RAM-tag design and CAM (Content Addressable Memory)-tag design. We adopt the CAM-tag style in our cache design because CAM cells have the functions of storage as well as data-matching, and thus can be easily used to realize the tag function in cache. The soft IP of cache controller implements the different writing strategies and block replacement methods. The input parameters of the cache generator include cache size, block size, information on set-associativity, writing strategy, replacement methods, etc. The output of the cache generator contains the RTL code for the soft IP and other necessary Models for the hard IP so that the generated cache can be mixed with other pure cell-based design modules during synthesis and placement-and-routing.

As the complexity of SoC increases rapidly, embedded memory becomes one of the critical components in current SoC design. In this thesis, we develop a memory generator so that users can easily integrate proper embedded memory circuits into SoC chips. The generator is based on a low-power multi-voltage-source memory architecture that partitions the complete memory into two parts to avoid unnecessary operations. In addition, we also address the modification of the memory architectures in order to provide more efficient data accessing in multimedia applications such as DCT, JPEG-2000 and 3D graphics. The developed memory generator can produce all the necessary files required in the traditional cell-based design flow, including behavior model, Synopsys library, LEF file, Spice netlists and layouts, so that the designers can easily utilize the generated memory units in their ASIC designs.

The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with conventional NAND based decoders. Two different column decoders, tree structure and NOR based predecoder, are provided in current version. Although only SRAM is implemented in this thesis, the memory generator platform is complete with all the necessary models required in the embedded design. In the future, other memories, such as cache, shift register, FIFO, stacks, ROM, register files, and content addressable memory, can be integrated in this memory generator platform.

Memory unit is one of the fundamental hardware components in system-on-chip (SoC) design, and takes a significant portion of total area cost. Although commercial memory compilers exist, they usually contains memory unit with single-port or dual ports. However, many SoC designs require memory units that support simultaneous multiple reads and writes. They cannot be efficiently generated using the existing memory compilers in the standard cell library. In this thesis, we develop a memory generator that can automatically produce the circuits of multi-port SRAM and all the necessary models required in the standard cell-based design flow. Compared to the design based on dual-port SRAM from memory compilers which usually consists of duplicated copies of SRAM units for supporting multiple write at the same, the proposed design has smaller area cost. Furthermore, we employ various low-power design concepts, including power-gating and adaptive body-bias, to reduce the dynamic and static power of the generated SRAM circuits. Experimental results show that the proposed multi-port SRAM generator can be used to synthesize low-power and low-area register file circuits that support multiple reads and writes at the same time.