Today's wireless transceivers require reference signals to translate received and transmitted signals to their desired frequencies. Therefore, they need frequency synthesizers which are typically based on phase-locked-loops (PLLs). Communication standards like GSM or Bluetooth necessiate that the PLLs put out oscillations with high spectral purity and accuracy. Additionally, the oscillation frequency must be adjustable very accurately at low transient time to account for occasional carrier frequency changes. So called Sigma-Delta-fractional-N frequency synthesizers are often employed to fulfil these requirements. However, the number and the locations of the poles of the control loop and hence the loop filter must be chosen properly. Unity gain frequency and phase margin have to be considered as well as the stringent frequency accuracy and the detailed origin of the spurious emissions. The design methodology proposed in this work is based on numerical optimization techniques, a high number of control loop poles and the use of Gm-C-biquads as loop filter building blocks.