Nesta dissertação é apresentada a aplicação da programação geométrica no projeto de uma fonte de tensão de referência de baixa tensão de alimentação que pode ser integrada em tecnologias padrões CMOS. Também são apresentados os resultados experimentais de um projeto da fonte de bandgap feito por um método de projeto convencional, cuja experiência motivou e ajudou ao desenvolvimento da formulação do programa geométrico proposta neste trabalho. O programa geométrico desenvolvido nesta dissertação otimiza o desempenho da fonte de bandgap e agiliza seu tempo de projeto. As expressões matemáticas que descrevem o funcionamento e as principais especificações da fonte de bandgap foram geradas e adaptadas ao formato de um programa geométrico. A compensação da temperatura, o PSRR, o consumo de corrente, a área, a tensão de saída e a sua variação por causa da tensão de offset do OTA, e a estabilidade são as principais especificações deste tipo de fonte de tensão de referência e fazem parte do programa geométrico apresentado neste trabalho. Um exemplo do projeto usando o programa geométrico formulado neste trabalho, mostra a possibilidade de projetar a fonte de bandgap em alguns minutos com erros baixos entre os resultados do programa geométrico e de simulação. / This work presents the application of geometric programming in the design of a CMOS low-voltage bandgap voltage reference source. Test results of a bandgap voltage reference designed via a conventional method are showed, this design experience motivated and helped to formulate the geometric program developed in this work. The geometric program developed in this work optimizes the bandgap source performance and speeds up the design time. The mathematical expressions that describe the bandgap source functioning and specifications were developed and adapted in the geometric program format. The temperature compensation, the PSRR, the current consumption, the area, the output voltage and its variations under the operational tranconductance amplifier offset voltage, and the stability are the main specifications of this type of bandgap reference source and they are included into the geometric program presented in this work. An example of the design using the geometric program formulated in this work, shows the possibility of designing the bandgap source in a few minutes with low errors between the geometric program results and the simulation results.

FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico / Nos Ãltimos anos, observa-se o surgimento e a rÃpida disseminaÃÃo do serviÃo VoIP, integrando-se ao mercado atual junto à telefonia convencional e Ãs redes celulares. Por ser uma alternativa tecnolÃgica que contribui para minimizar ustos, assiste-se a uma preferÃncia crescente por fazer fegar a voz atravÃs das redes IP. O HSDPA, como sistema celular, permite a transmissÃo de dados em alta velocidade, aumenta a largura de banda da rede e abre novas possibilidades de serviÃos multimÃdia, como o VoIP que utiliza a transmissÃo em banda larga para telefones mÃveis. Exige-se, porÃm, um considerÃvel esforÃo de anÃlise deste serviÃo, pois o atraso inerente a esse sistema à um desafio para a garantia de qualidade de voz. Estes fatos justificam, conseqÃentemente, um esforÃo de anÃlise que se detenha sobre a qualidade de voz no VoIP sobre o HSDPA. Para avaliar a qualidade de voz, neste estudo aplica-se o mÃtodo MOS, que faz corresponder valores numÃricos a categorias como medidas de qualidade e inteligibilidade da voz transmitida, obtendo-se esses dados de forma objetiva e subjetiva. O processo de avaliaÃÃo dividiu-se em etapas de acordo com cada metodologia, seguindo recomendaÃÃes tÃcnicas e atravÃs de simulaÃÃes computacionais dinÃmicas. Na avaliaÃÃo objetiva, utilizou-se o algoritmo PESQ para obtenÃÃo do conceito MOS, enquanto que na avaliaÃÃo subjetiva, arquivos de voz com certo percentual de erro foram colocados em um endereÃo na Internet para escuta e atribuiÃÃo de nota MOS, baseada na percepÃÃo do usuÃrio ouvinte. Os resultados mostraram que os dois mÃtodos de avaliaÃÃo obtiveram conceitos de qualidade satisfatÃrios, que o QoS nas simulaÃÃes à estÃvel e positivo, que uma boa qualidade para os arquivos de voz e a provÃvel satisfaÃÃo dos usuÃrios do serviÃo VoIP sobre o sistema celular HSDPA à garantida para uma taxa de 2% de FER. Finalmente, mostra-se que a metodologia objetiva garante a obtenÃÃo de notas MOS aproximadas da subjetiva, evitando o Ãrduo trabalho de fazerem-se ouvir diversos arquivos de voz por uma quantidade significativa de usuÃrios para ser vÃlida estatisticamente. / In recent years, we can observe the development and fast dissemination of VoIP services, being integrated by the present market, beside conventional telephony and cellular networks. For being a technological alternative that contributes to minimize costs, we see an increasing preference for voice transmission through IP networks. HSDPA, as a cellular system, allows high speed data transmission,increases the network width of band and creates new possibilities for multimedia services, as VoIP that transmits in wideband to mobile telephones. The delay inherent to this system, however, is a challenge for the need to assure good quality of voice transmissions, demanding a considerable effort of analysis of this service.These facts justify a study that focus on the quality of voice in VoIP over HSDPA.To evaluate the voice quality, in this study, we applied MOS method that makes numerical values correspond to categories like quality and intelligibility of transmitted voice, getting these data through objective and subjective methodologies. The evaluation process was divided in fases according to the characteristics of each methodology and to technical recommendations, and was done through dynamic computational simulations. For objective evaluation process,algorithm PESQ was employed to obtain MOS concepts, whereas, for subjective evaluation, voice files with a percentage of error have been placed in Internet for listening and for the attribution of MOS concepts based in the perception of the listener. The results of this research show that both evaluation methods got satisfactory concepts of quality, that QoS is steady and positive in the simulations, that a good quality for the voice files and the probable satisfaction of the users of the VoIP service on cellular system HSDPA is guaranteed for 2% FER rate. Finally, it shows that MOS concepts produced by objective methodology were close enough to those given by subjective evaluation to dispense with the arduous work of making diverse voice files to be heard and subjectively evaluated by a statisticaly valid amount of users.

Les produits issus des technologies Silicium tendent à exploiter au maximum les performancesdes transistors MOS tout en les soumettant à des profils de mission très agressifs du point de vuede la fiabilité. Les concepteurs sont ainsi à la recherche du meilleur compromis entre performanceet fiabilité.Historiquement, l’étude de la fiabilité du transistor MOS et le développement des modèlessous jacents ont été menés sur la base de contrainte de vieillissement statique. Avec le développementdes produits à hautes performances dans le domaine de la radiofréquence (RF), laquestion de la fiabilité pour ce type d’application se pose. Ainsi, une extension des modèles defiabilité doit être réalisée afin de quantifier le vieillissement des paramètres clés RF soumis àdes contraintes statiques mais également RF. C’est cette extension de la fiabilité des transistorsMOS dans le domaine RF qui constitue le sujet de ce travail de thèse.Dans ce manuscrit, le fonctionnement du transistor MOS est décrit et sa fiabilité est introduite.Les différents mécanismes de dégradation sont étudiés et leurs modèles associés décrits.Sont ensuite présentés un banc de mesure et une méthodologie nécessaire à l’étude du vieillissementdes transistors dans le domaine RF, ainsi qu’à l’extension des modèles de fiabilité audomaine RF. / Products using nowadays silicon technology are generally targeting aggressive specificationsand push the developers to determine the best compromise between performance and reliability.Main front-end degradation mechanisms are historically studied and modeled under static stressconditions and focus on the static MOS transistor parameters.With the development of product targeting high performances in the radio frequency (RF)domain, the reliability is becoming a first order concern. Thus an extension of the actual staticreliability models must be done to quantify the aging of key RF parameters under static andRF stress. In this context, this work focuses on the extension of the MOS transistor reliabilityregarding the study of RF parameters and also the application of RF stress.After describing the MOS transistor properties, the reliability aspect is introduced and theemphasis is put on the different degradation mechanisms and their associated models. Thisallows the development of an experimental setup and the required methodology to investigatethe device aging in the RF domain and to extend actual static models.

Pour la détermination des contraintes thermomécaniques au niveau du silicium, les capteurs piézorésistifs (en rosette) composés de 4nMOS et 4pMOS ont été développés et embarqués dans des produits de la microélectronique.Les relations caractéristiques liant les grandeurs piézorésistives, électriques et mécaniques ont été établies.La détermination des grandeurs piézorésistives nécessite un test de calibration effectué ici à l’aide d’une machine de flexion quatre-points. Cette machine a été conçue et fabriquée dans le cadre de cette thèse et permet d’appliquer une contrainte uniforme uni-axiale dans l’échantillon de silicium et de déterminer ainsi les trois coefficients piézorésistifs.Les capteurs intégrés sur différentes technologies telles que CMOS65, BiCMOS55, CMOS40, BSI140 et PIC25 ont été calibrés avec cette machine.Ces capteurs MOS ont été utilisés dans les cas d’études des contraintes induites par le TSV (technologie CMOS65), par la mise en boitier avec un empilement 3D (technologie CMOS65) et un empilement 2D (technologie BiCMOS55).Les résultats donnent des composantes de contraintes (σyy, σzz) qui ne sont pas en bonne corrélation avec les résultats de simulations. Les réponses électriques des MOS orientés à 90° (direction [010]) par rapport à l’axe des x (direction [100]) sont mises en question, car le coefficient (π12) obtenu à partir de ce MOS agit directement sur les deux composantes de contraintes.D’autre part, les variations de contraintes dans la zone des capteurs, les variabilités inter-puces et inter-plaques perturbent les résultats.Intégrées dans la même structure de test de la technologie CMOS40, différents composants ont été étudiés, notamment les transistors MOS rosette, la structure bandgap et les résistances poly-Si qui ont aussi été calibrés.Une étude de la contrainte thermomécanique induite par la mise en boitier de cette technologie a révélé un fort impact sur les réponses de sortie (mobilité des MOS, tension bandgap).Par une étude de minimisation paramétrique, cet impact a été réduit en agissant sur les dimensions géométriques des constituants et les propriétés matériaux de la résine de moulage.Ces résultats montrent que les MOS en rosette peuvent être utilisés comme capteurs de contraintes mais avec une efficacité limitée. L’utilisation des résistances actives comme capteurs de contraintes est donc envisageable. Par contre, ces MOS peuvent être utilisés pour déterminer l’impact des contraintes sur le fonctionnement de la puce. / For the thermomechanical stress assessment in silicon, piezoresistive sensors (in rosette) composed of 4nMOS and 4pMOS were developed and embedded into microelectronic products.The characteristic relations between piezoresistive, electrical and mechanical quantities were established.Piezoresistive quantities were identified thanks to a four-points bending calibration machine. This machine was designed and fabricated in the frame of this PhD and enables applying a known uniform uniaxial stress into silicon sample and then calculating the three piezoresistive coefficients.The sensors embedded into different technologies such as CMOS65, BiCMOS55, CMOS40, BSI140 and PIC25 were calibrated with this machine.These MOS sensors were used for studying stresses induced by TSV (CMOS65 technology), by packaging with 3D stacking (CMOS65 technology) and 2D stacking (BiCMOS55 technology).The results give stress components (σyy, σzz) which are not in a good agreement with simulation results. Electrical responses of the MOS oriented at 90° ([010] direction with respect to the x axis ([100] direction)) are questioned because the coefficients (π12) obtained from this MOS acts directly on the two components.In addition, stress variations in sensors area, as well as inter-chips and inter-wafers variabilities disturb the results.Integrated into the same test chip of the CMOS40 technology, different structures were studied, namely the MOS transistors, the bandgap structure and the poly-Si resistances which were also calibrated.For this technology, a study of thermomechanical stress induced by packaging revealed a significant impact on the output responses (MOS mobility, bandgap voltage). Through a minimization parametric study, this impact was reduced by controlling the geometrical dimensions of components and the material properties of the moulding compound.These results show that, MOS rosettes can be used as stress sensors but with a limited efficiency. The use of active resistances as stress sensors is therefore envisaged. However, these MOS can be used to study the impact of stresses on the chip operation.

Orientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2015. / Este trabalho tem como escopo o projeto e implementação de indutores ativos integrados em tecnologia CMOS para operação em circuitos integrados de r'adio frequência. Tais sistemas demandam por indutores passivos integrados, sendo que estes geralmente apresentam baixa indutância, baixo fator de qualidade, e tamanhos relativamente grandes. Estes fatores são limitantes no projeto de circuitos integrados. Como alternativa, indutores ativos integrados têm sido propostos, com o uso de circuitos que emulam o efeito do indutor passivo convencional. Estes circuitos apresentam menor dimens¿ao, possibilidade de ajustes no valor da indut¿ancia, da frequ¿encia de opera¸c¿ao, do fator de qualidade, ao custo de consumo de pot¿encia DC e um relativo aumento no ru'ýdo total do sistema. Al'em de um profundo estudo, quatro topologias distintas de indutores ativos integrados foram abordadas e projetadas, em seguida foi projetado um VCO aplicando dois indutores ativos como ressonadores. Uma an'alise a n'ývel de projeto utilizando a t'ecnica de-embedding 'e aplicada no projeto de um indutor ativo. Os modelos dos componentes utilizados s¿ao baseados na biblioteca CMOS em alta frequ¿encia da foundry austr'ýaca AMS. / This study aimed to design and implement integrated active inductors in CMOS technology for operation in integrated radio frequency circuits. These systems demand for integrated passive inductors, and these usually have low inductance, low quality factor, and relatively large sizes. These factors are limiting in integrated circuit design. As an alternative integrated active inductors have been proposed, with the use of circuits that emulate the effect of conventional passive inductor. These circuits have smaller, the possibility for tuning the inductance value, the operation frequency, quality factor, at the cost of DC power consumption and a relative increase in total system noise. In addition to a thorough study, four different topologies ofintegrated active inductors were approached and designed, then was design a VCO applying two active inductors as resonators. An examination at the design level using the de-embedding technique is applied in the design of an active inductor. The models of the components used are based on CMOS library at high frequency of the Austrian foundry AMS.

Orientador: Prof. Dr. Carlos Eduardo Capovilla / Dissertação (mestrado) - Universidade Federal do ABC, Programa de Pós-Graduação em Engenharia Elétrica, 2017.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

.Aujourd’hui, la course à la miniaturisation a engendré de nouveaux défis dans l’industrie microélectronique. En plus de la forte concurrence que subissent les fabricants de composants, de nouvelles contraintes liées à la fiabilité des dispositifs se sont imposées. En effet, le passage d’une technologie « tout silicium » relativement simple à une technologie high-k/grille métal plus complexe, a entrainé une forte réduction des marges de fiabilité des oxydes de grille. A ce titre, Il est devenu nécessaire d’investiguer de nouvelles approches pouvant offrir davantage de gain en durée de vie pour les transistors MOS. C’est dans ce contexte que s’inscrit ce travail de thèse. Dans un premier temps, une présentation des différentes méthodes de caractérisations adaptées à l’étude du vieillissement des dispositifs high-k à grille métallique est faite. Dans ce cadre, des techniques de mesures rapides (type FAST BTI) sont mises en place et adaptée à l’étude du claquage d’oxyde. Ensuite, afin de démontrer que les durées de vie estimées aujourd’hui sont pessimistes, une étude de fiabilité portant sur la compréhension et la modélisation du mécanisme de TDDB (Time Dependent Dielectric Breakdown) sur les technologies avancées à base d’oxyde IL/high-k est présentée. Enfin, le manuscrit se focalise sur un certain nombre d’axes de travail qui pourraient permettre de dégager une marge significative sur la durée de vie TDDB. / .Today, in the race for miniaturization, the microelectronics industry faces new challenges. In addition to the strong competition of other component manufacturers, new constraints related to the reliability of devices have emerged. Indeed, the transition from the "all silicon" technology relatively simple to the high-k/metal gate technology has generated a reduction in reliability margins of gate oxides. As such, it becomes necessary to investigate new approaches that can provide more gain in lifetime for the MOS transistors. In this respect, this work gives firstly an overview of different methods of characterization used for the study of aging high-k metal gate devices. In this context, the need to develop and implement new fast techniques essential to the study of the oxide breakdown is exposed. Afterwards, in order to show that the estimated lifetimes today are pessimistic, we presented a reliability study based on understanding and modeling the mechanism of TDDB (Time Dependent Dielectric Breakdown) on advanced high-k/metal gate stacks based technology. Finally, the manuscript focuses on a number of investigation areas that could provide a significant margin for the TDDB lifetime.

Neste trabalho, investigou-se capacitores MOS fabricados sobre superfícies irregulares contendo formas retangulares periódicas com 100 nm de altura, obtidas a partir de corrosão por plasma localizadas. Os óxidos de porta com 4,5 nm de espessura foram crescidos em ambientes ultrapuros de O2 ou pirogênico a fim de comparar a uniformidade de cobertura sobre os degraus verticais dos perfis retangulares. Foi mostrado que a oxidação pirogênica ou convencional na temperatura de 850 ºC permite obter óxidos de porta sobre degraus com altura de 100nm com baixa corrente de fuga e alto campo de ruptura. Esse comportamento pode ser interpretado como óxidos de porta perfeitamente amoldados sobre os degraus de 100nm de altura. O impacto deste resultado é agora a possibilidade de implementar óxidos de porta para transistores de porta envolvente e FinFETs. / In this work, it was investigated MOS capacitors fabricated onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching onto silicon wafer surfaces. 4.5-nm gate oxide growth was performed in ultrapure dry O2 or pyrogenic environments in order to compare the coverage uniformity at the step edges of rectangular shapes defined onto the silicon surfaces. It was shown that pyrogenic and conventional oxidation at 850 ºC allows one to obtain gate oxides on 100nm-stepped silicon surfaces with low leakage current and high dielectric breakdown field. This behavior can be understood as highly conformal gate oxides over silicon steps with height of 100 nm. The impact of this result is now the feasibility of implementing gate oxides for surrounding gate transistors (SGT\'s) and FinFETs.

This work builds on a semester project 2 from the winter semester of this academic year. The aim of this thesis is the design of converter using semiconductor components based on SiC technology. This converter is used in the construction of quick charger for electric vehicles. The design of this converter must be based on the requirements for compliance voltage safety. It describes the design of power components used in the construction of this facility, the determination of their losses and determines the overall efficiency of the converter. There is also proposed mathematical model of high-frequency transformer and made his simulation in Matlab-Simulink.