Bielefeld, University, Diss., 2003.

Stuttgart, Universiẗat, Diss., 2002.

Stuttgart, Universiẗat, Diss., 2002.

Darmstadt, Techn. Universiẗat, Diss., 2001.

Darmstadt, Techn. Universiẗat, Diss., 2002.

Zugl.: Dortmund, University, Diss., 2003.

München, Techn. Universiẗat, Diss., 2003.

Freiburg (Breisgau), Universiẗat, Diss., 2004.

abstract: Wireless video sensor networks has been examined and evaluated for wide range of applications comprising of video surveillance, video tracking, computer vision, remote live video and control. The reason behind importance of sensor nodes is its ease of implementation, ability to operate in adverse environments, easy to troubleshoot, repair and the high performance level. The biggest challenges with the architectural design of wireless video sensor networks are power consumption, node failure, throughput, durability and scalability. The whole project here is to create a gateway node to integrate between "Internet of things" framework and wireless sensor network. Our Flexi-Wireless Video Sensor Node Platform (WVSNP) is a low cost, low power and compatible with traditional sensor network where the main focus was on maximizing throughput or minimizing node deployment. My task here in this project was to address the challenges of video power consumption for wireless video sensor nodes. While addressing the challenges, I performed analysis of predicting the nodes durability when it is battery operated and to choose appropriate design parameters. I created a small optimized image to boot up Wandboard DUAL/QUAD board, capture videos in small/big chunks from the board. The power analysis was performed for only capturing scenarios, playback of reference videos and, live capturing and realtime playing of videos on WVSNP player. Each sensor node in sensor network are battery operated and runs without human intervention. Thus to predict nodes durability, for dierent video size and format, I have collected power consumption results and based on this I have provided some recommendation of HW/SW architecture. i / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

In the past, multimedia technology focused mainly on designing high quality audio and graphical imagery as well as providing adequate performance levels that the users demand for multimedia applications. However, the concept of multimedia has expanded into New-Media that involves variety use of multimedia data in consumer-oriented applications, such as video conferencing, virtual reality, and multimedia games with 3-D effect in video and audio. As the demands for multimedia applications increase, vendors have come up with new cost-effective microprocessor designs to satisfy the complexity of new media processing. One of the most efficient methods is to incorporate the special-purpose multimedia processor into a general-purpose processor, thereby offering multimedia-related functions at a small cost. Most effective way to integrate the two different processors is to extend the existing instruction set into a multimedia-oriented Instruction Set Architecture, called Media ISA Extension. Currently, many microprocessor vendors have produced variety of general-purpose processors with multimedia extensions. This thesis aims to provide the overall design philosophy behind Media ISA Extension and its effect on the overall performance of a general-purpose processor. In particular, Sun Microsystems' Visual Instruction Set (VIS) media extension of UltraSPARC-V9 is studied. On the average, VIS provides a speed-up of 3 to 4 for various multimedia applications. This performance improvement comes from the considerable reduction in the number of instructions executed due to Single Instruction Multiple Data (SIMD) execution style of VIS media extensions. To examine how VIS improves multimedia performance, the thesis studies the design concept, benefits and limitations of VIS extensions, and the performance of various multimedia applications with and without VIS extension. Finally, the possible architectural modifications to the VIS extension for further performance enhancement are suggested. / Graduation date: 2000