Enormous demands for fast and low-power computing and memory building blocks for consumer electronics, such as smartphones or tablets, have led to the emergence of silicon nanowire transistors a decade ago. Along with the Si-based nanotechnology, the silicon compatible optical and chemical sensing applications have boosted the research on hybrid devices that combine the organic and inorganic materials. Apart from the revolution in the device dimensions, the rapid growth of artificial intelligence in the software industry brunch requires the next generation’s computers with the revolutionized hybrid device architecture. Implementing such new devices can effectively perform machine learning tasks without the massive consumption of energy. The hybrid Si nanowire devices have an excellent capability to replace the conventional computing element by providing new functionalities of combined materials to the traditional transistor devices preserving the advantage of CMOS technology. A goal of this thesis is to develop functional hybrid Si nanowire-based transistors modulated by the stimuli-dependent gate to go beyond the current digital building blocks. The hybrid devices converge semiconductor channel and various materials from organic molecules to silicate composite as a gate of the transistor. External stimuli change the electronic state of the gate materials which is transformed to the gate potential of the transistors. First, this thesis studies the electronic characteristics of the Si nanowire FETs under the optical stimulus. Optical stimulus induces the strong conductance change on bare Si nanowire FETs. Under the light with low power intensity, the transistor shows an unconventional negative photoconductance (NPC) which is dependent on the doping concentration of the nanowire and the wavelength of the incident light. The dopants ions and surface states cause photo-generated hot electrons trapping which restricts conventional photoconductance in the semiconductor. In the hybrid device, however, the gate material on the Si dioxide layer plays a significant role in the optoelectronic modulation of the FET device. This thesis demonstrates that an organic photochromic material, porphyrin, wrapping around the nanowire channel acts as an optical gate of the Si nanowire transistor. The diffusive property of electrons in the molecular film decides the optical switching dynamics and efficiency. Further, this thesis introduces new functional gate material, sol-gel derived ion-doped silicate film, based on the availability of stimulus-dependent gate modulation. This amorphous and transparent silicate film shows memristive property due to the ionic redistribution in the film under bias condition. Interestingly, the sol-gel film-coated Si nanowire FETs the devices show a double gate effect cooperating with a back gate under light illumination which is due to the channel separation in the fin structure of the nanowire. In addition, the sol-gel silicate film-coated Si nanowire transistor emulates the neuronal plasticity with pulsed gate stimulation, namely “neurotransistor.” Because of the mobile ions in the silicate film, the transistor has a short-term memory and mimics membrane potential change of the neuron cell. The neurotransistor could be used as a computing node in the physical neural network for hardware machine learning. This work demonstrates that the physical properties of the gate material decide the transfer characteristics and time-dependent dynamics of the hybrid Si nanowire transistors. The optical and neuromorphic gate features of the hybrid transistors would accelerate the advancement of an optical or brain-like computing machine.

Neuromorphic engineering is the research field dedicated to the study and design of brain-inspired hardware and software tools. Recent advances in emerging nanoelectronics promote the implementation of synaptic connections based on memristive devices. Their non-volatile modifiable conductance was shown to exhibit the synaptic properties often used in connecting and training neural layers. With their nanoscale size and non-volatile memory property, they promise a next step in designing more area and energy efficient neuromorphic hardware. My research deals with the challenges of harnessing memristive device properties that go beyond the behaviors utilized for synaptic weight storage. Based on devices that exhibit non-linear state changes and volatility, I present novel architectures and algorithms that can harness such features for computation. The crossbar architecture is a dense array of memristive devices placed in-between horizontal and vertical nanowires. The regularity of this structure does not inherently provide the means for nonlinear computation of applied input signals. Introducing a modulation scheme that relies on nonlinear memristive device properties, heterogeneous state patterns of applied spatiotemporal input data can be created within the crossbar. In this setup, the untrained and dynamically changing states of the memristive devices offer a useful platform for information processing. Based on the MNIST data set I'll demonstrate how the temporal aspect of memristive state volatility can be utilized to reduce system size and training complexity for high dimensional input data. With 3 times less neurons and 15 times less synapses to train as compared to other memristor-based implementations, I achieve comparable classification rates of up to 93%. Exploiting dynamic state changes rather than precisely tuned stable states, this approach can tolerate device variation up to 6 times higher than reported levels. Random assemblies of memristive networks are analyzed as a substrate for intrinsic computation in connection with reservoir computing; a computational framework that harnesses observations of inherent dynamics within complex networks. Architectural and device level considerations lead to new levels of task complexity, which random memristive networks are now able to solve. A hierarchical design composed of independent random networks benefits from a diverse set of topologies and achieves prediction errors (NRMSE) on the time-series prediction task NARMA-10 as low as 0.15 as compared to 0.35 for an echo state network. Physically plausible network modeling is performed to investigate the relationship between network dynamics and energy consumption. Generally, increased network activity comes at the cost of exponentially increasing energy consumption due to nonlinear voltage-current characteristics of memristive devices. A trade-off, that allows linear scaling of energy consumption, is provided by the hierarchical approach. Rather than designing individual memristive networks with high switching activity, a collection of less dynamic, but independent networks can provide more diverse network activity per unit of energy. My research extends the possibilities of including emerging nanoelectronics into neuromorphic hardware. It establishes memristive devices beyond storage and motivates future research to further embrace memristive device properties that can be linked to different synaptic functions. Pursuing to exploit the functional diversity of memristive devices will lead to novel architectures and algorithms that study rather than dictate the behavior of such devices, with the benefit of creating robust and efficient neuromorphic hardware.

The rapid proliferation of the Internet of Things (IoT) devices and the growing demand for intelligent systems have driven the development of low-power, compact, and efficient machine learning solutions. Deep neural networks (DNNs) have become state-of-the-art algorithms in various applications, such as face recognition, object detection, and speech recognition, due to their exceptional accuracy. In terms of edge devices, it is ideal to execute these algorithms locally on devices rather than on servers to mitigate data transfer latency and address privacy concerns. Reducing power consumption and enhancing energy efficiency becomes crucial, as mobile and wearable devices typically have limited battery capacity. Low-power consumption can extend battery life, reduce recharging cycles, and thus decrease maintenance costs. Ultra-Low-power AI hardware has increasingly garnered attention due to its potential to enable numerous compelling applications. This technology can serve as an always-on wake-up module, such as keyword spotting and visual wake-up, to facilitate hierarchical data processing. Addi-tionally, it can be employed in security and surveillance applications on battery-powered cameras and miniaturized drones. Various techniques to reduce power consumption have been proposed at individual levels, encompassing algorithms, architecture, and circuits. Application-oriented ultra-low-power AI hardware design incorporating full-stack optimization can exploit unique features in specific tasks and further minimize power consumption. This thesis presents my research on algorithm-hardware co-design for ultra-low-power hardware for AI applications. Chapter 2 to 5 list my past works. The first work implements a spiking neural network classifier that leverages fully event-driven architecture to reduce power consump-tion while the input activity is low. The second work presents an end-to-end keyword spotting system featuring divisive energy normalization for both internal and external noise robustness. The third work shows a digital in-memory-computing macro utilizing approximate arithmetic hardware for better area and energy efficiency. The last work demonstrates an automatic speech recognition chip featuring bio-inspired neuron model, digital in-memory-computing hardware with time-sharing arithmetic units, and fully pipelined architecture for low power consumption and real-time processing.

Continuing advances with VLSI have enabled engineers to build high performance computer systems to solve complex problems. The real-world problems and tasks like pattern recognition, speech recognition, etc. still remain elusive to the most advanced computer systems today. Many advances in the science of computer design and technology are coming together to enable the creation of the next-generation computing machines to solve real-world problems, which the human brain does with ease. One such engineering advance is the field of neuromorphic engineering, which tries to establish closer links to biology and help us investigate the problem of designing better computing machines. A chip built with the principles of neuromorphic engineering is called as neuromorphic chip. Neuromorphic chip aims to solve real-world problems. As the complexity of the problem increases, the computation capability of these chips can become a limitation. In order to improve the performance and accomplish a complex task in the real-world, many such chips need to be integrated into a system. Hence, efficiency of such a system depends on effective inter-chip communication. Here, the work presented aims at building a message-passing network (Digital Fabric) simulator, that integrates many such chips. Each chip represents a binary event-based unit called spiking analog cortical module. The inter-chip communication protocol employed here is called as Address Event Representation. Here, the Digital Fabric is built in three revisions, with different architectures being considered in each revision. The complexity is increased at each iteration stage. The experiments performed in each revision test the performance of such configuration systems and results proves to lay a foundation for further studies. In the future, building a high level simulation model will assist in scaling and evaluating various network topologies.