Frequency synthesizers are essential components for modern wireless and wireline communication systems as they provide the local oscillator signal required to transmit and receive data at very high rates. They are also vital for computing devices and microcontrollers as they generate the clocks required to run all the digital circuitry responsible for the high speed computations. Data rates and clocking speeds are continuously increasing to accommodate for the ever growing demand on data and computational power. This places stringent requirements on the performance metrics of frequency synthesizers. They are required to run at higher speeds, cover a wide range of frequencies, provide a low jitter/phase noise output and consume minimum power and area. In this work, we present new techniques and architectures for implementing high speed frequency synthesizers which fulfill the aforementioned requirements. We propose a new architecture and design approach for the realization of wideband millimeter-wave frequency synthesizers. This architecture uses two-step multi-order harmonic generation of a low frequency phase-locked signal to generate wideband mm-wave frequencies. A prototype of the proposed system is designed and fabricated in 90nm Complementary Metal Oxide Semiconductor (CMOS) technology. Measurement results demonstrated that a very wide tuning range of 5 to 32 GHz can be achieved, which is costly to implement using conventional techniques. Moreover the power consumption per octave resembles that of state-of-the art reports. Next, we propose the N-Push cyclic coupled ring oscillator (CCRO) architecture to implement two high performance oscillators: (1) a wideband N-Push/M-Push CCRO operating from 3.16-12.8GHz implemented by two harmonic generation operations using the availability of different phases from the CCRO, and (2) a 13-25GHz millimeter-wave N-Push CCRO with a low phase noise performance of -118dBc/Hz at 10MHz. The proposed oscillators achieve low phase noise with higher FOM than state of the art work. Finally, we present some improvement techniques applied to the performance of phase locked loops (PLLs). We present an adaptive low pass filtering technique which can reduce the reference spur of integer-N charge-pump based PLLs by around 20dB while maintaining the settling time of the original PLL. Another PLL is presented, which features very low power consumption targeting the Medical Implantable Communication Standard. It operates at 402-405 MHz while consuming 600microW from a 1V supply.

Impedance measurement as a function of frequency is being increasingly used for the detection of organic molecules. The main building block required for this is a sinusoidal oscillator whose frequency can be varied in the range of a few KHz to tens of MHz. The thesis describes the design of Integrated CMOS Oscillator Circuits. There are 2 designs presented in the thesis, one of which is based on the Wien Bridge and the other, on an LC architecture. They provide both in-phase and quadrature outputs needed for the determination of the real and imaginary parts of complex impedances. The inductor in the LC tank is realized by gyration of a capacitor. This needs two variable transconductance elements. Linear transconductance elements with decoupled transconductance gm and output conductance go is presented. A novel circuit for detecting and controlling the amplitude of oscillation is described. A current mode technique to scale the capacitance is also discussed. Since this oscillator is used in an inexpensive hand-held instrument, both power consumption and chip area must be minimized. A comparison between the Wien Bridge and the LC tank based oscillator is presented. Simulation results pertaining to the design of the different blocks of the circuit are made available. / text

No description available.

by Leung Pui-tang. / Parallel title in Chinese characters. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1988. / Bibliography: leaves 92-94.

by Tsui Wan-lam. / Chinese title in romanization: Zi you dian zi ji guang fang da qi ji zhen dang qi di jing dian li lun. / Thesis (Ph.D.)--Chinese University of Hong Kong, 1987. / Bibliography: leaves 93-95.

by Fan Chun-Wah. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 90-[91]). / Abstract also in Chinese. / Chapter CHAPTER 1: --- INTRODUCTION --- p.1 / Chapter CHAPTER 2: --- BACKGROUND OF INJECTION LOCKING --- p.3 / Chapter 2.1 --- Basics of Injection Locking --- p.3 / Chapter 2.2 --- Analytical Methods for Injection Locking --- p.6 / Chapter 2.2.1 --- Analysis of Fundamental Mode Injection Locking --- p.6 / Chapter 2.2.2 --- Analysis of Ha rmonic/Subharmonic Injection Locking --- p.9 / Chapter 2.4 --- Numerical Methods --- p.11 / Chapter CHAPTER 3: --- THE VOLTERRA SERIES METHOD FOR NONLINEAR CIRCUIT ANALYSIS --- p.13 / Chapter 3.1 --- Volterra Expansion --- p.14 / Chapter 3.2 --- Evaluation of Nonlinear Transfer Function --- p.16 / Chapter 3.2.1 --- Probing Method --- p.16 / Chapter 3.2.2 --- Nonlinear Current Method --- p.17 / Chapter 3.2.3 --- Higher order nonlinear current --- p.20 / Chapter 3.2.4 --- Voltage response by using nonlinear transfer function --- p.20 / Chapter 3.3 --- Advantage of Volterra Series --- p.21 / Chapter 3.4 --- Volterra Series Simulator(VSS) Implementation --- p.22 / Chapter 3.4.1 --- Admittance Matrix Formulation --- p.22 / Chapter 3.4.2 --- Evaluation of Nonlinear Response --- p.26 / Chapter 3.4.3 --- Local Cache and Global Cache --- p.26 / Chapter 3.4.4 --- Components Library --- p.27 / Chapter 3.4.5 --- Verification of Simulator --- p.27 / Chapter CHAPTER 4: --- VOLTERRA SERIES GENERAL INJECTION-LOCKED OSCILLATOR FORMULATION --- p.28 / Chapter 4.1 --- Volterra Series Approach to Analysis of Autonomous System --- p.29 / Chapter 4.1.1 --- Chua and Tang's work --- p.29 / Chapter 4.1.2 --- Cheng and Everard's work --- p.29 / Chapter 4.1.3 --- Huang and Chu 's work --- p.30 / Chapter 4.2 --- A Novel Approach --- p.33 / Chapter 4.3 --- Derivation of Determining Equation --- p.35 / Chapter 4.4 --- Injection Lock vector and circuit synthesis --- p.38 / Chapter 4.5 --- Modification to Volterra Series Simulator (VSS) --- p.40 / Chapter CHAPTER 5: --- CIRCUIT MODELING AND PARAMETER EXTRACTION --- p.42 / Chapter 5.1 --- Forward-Bias Gate Measurement --- p.42 / Chapter 5.2 --- Low FREQUENCY S-PARAMETER MEASUREMENT --- p.50 / Chapter 5.3 --- Parameter Extraction from High Frequency S-Parameter Data --- p.52 / Chapter 5.3.1 --- Direct Extraction Method --- p.52 / Chapter 5.3.2 --- Estimation of lead inductance --- p.56 / Chapter 5.4 --- Large Signal Characterization and Extraction --- p.59 / Chapter 5.4.1 --- Large Signal Model --- p.59 / Chapter 5.4.2 --- Extraction of g2 and g3 --- p.60 / Chapter 5.5 --- Equivalent circuit model for inductor and capacitor --- p.67 / Chapter CHAPTER 6: --- APPLICATION TO 1/3 ANALOG FREQUENCY DIVIDER --- p.68 / Chapter 6.1 --- Oscillator design by negative resistance approach --- p.68 / Chapter 6.2 --- Simulation of Free Running Oscillation by VSS --- p.73 / Chapter 6.3 --- Simulation of injection locked oscillator by VSS --- p.75 / Chapter 6.4 --- Injection Locking Experiment --- p.77 / Chapter 6.5 --- Injection Lock Vector --- p.80 / Chapter CHAPTER 7: --- CONCLUSIONS AND RECOMMENDATIONS FOR FUTURE WORK --- p.85 / Chapter 7.1 --- Conclusions --- p.85 / Chapter 7.2 --- Recommendations for Future Work --- p.86 / APPENDIX 1: REFERENCES --- p.87 / APPENDIX 2: PUBLICATION --- p.91

Chee Shiu Chung = 阻尼振子的線空間結構與哈密頓理論 / 朱兆中. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2003. / Includes bibliographical references (leaves 88). / Text in English; abstracts in English and Chinese. / Chee Shiu Chung = Zu ni zhen zi de xian kong jian jie gou yu ha mi dun li lun / Zhu Zhaozhong. / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Conservative Systems --- p.4 / Chapter 2.1 --- General Formalism --- p.4 / Chapter 2.2 --- One Simple Harmonic Oscillator --- p.7 / Chapter 2.3 --- Two Coupled Harmonic Oscillators --- p.9 / Chapter 3 --- Dissipative Systems --- p.12 / Chapter 3.1 --- Elimination of Bath --- p.12 / Chapter 3.2 --- One Oscillator with Dissipation --- p.16 / Chapter 3.3 --- Two Oscillators with Dissipation --- p.19 / Chapter 4 --- Eigenvector Expansion and Bilinear Map --- p.21 / Chapter 4.1 --- Formalism --- p.21 / Chapter 4.2 --- Inner Product and Bilinear Map --- p.23 / Chapter 4.3 --- Normalization and Phase --- p.25 / Chapter 4.4 --- Matrix Representation --- p.25 / Chapter 4.5 --- Duality --- p.28 / Chapter 5 --- Applications and Examples of Eigenvector Expansion --- p.31 / Chapter 5.1 --- Single Oscillator --- p.31 / Chapter 5.2 --- Two Oscillators --- p.32 / Chapter 5.3 --- Uneven Damping --- p.33 / Chapter 6 --- Time Evolution --- p.36 / Chapter 6.1 --- Initial-Value Problem --- p.36 / Chapter 6.1.1 --- Green's Function --- p.37 / Chapter 6.2 --- Sum Rules --- p.39 / Chapter 7 --- Time-Independent Perturbation Theory --- p.41 / Chapter 7.1 --- Non-degenerate Perturbation --- p.41 / Chapter 7.2 --- Degenerate Perturbation Theory --- p.46 / Chapter 8 --- Jordan Block --- p.48 / Chapter 8.1 --- Jordan Normal Basis --- p.48 / Chapter 8.1.1 --- Construction of Basis Vectors --- p.48 / Chapter 8.1.2 --- Bilinear Map --- p.50 / Chapter 8.1.3 --- Example of Jordan Normal Basis --- p.55 / Chapter 8.2 --- Time Evolution --- p.56 / Chapter 8.2.1 --- Time Dependence of Basis Vectors --- p.56 / Chapter 8.2.2 --- Initial-Value Problem --- p.58 / Chapter 8.2.3 --- Green's Function --- p.59 / Chapter 8.2.4 --- Sum Rules --- p.60 / Chapter 8.3 --- Jordan Block Perturbation Theory --- p.61 / Chapter 8.3.1 --- Lowest Order Perturbation --- p.61 / Chapter 8.3.2 --- Higher-Order Perturbation --- p.65 / Chapter 8.3.3 --- Non-generic Perturbations --- p.66 / Chapter 8.4 --- Examples of High-Order Criticality --- p.66 / Chapter 8.4.1 --- Fourth-order JB --- p.67 / Chapter 8.4.2 --- Third-order JB --- p.74 / Chapter 8.4.3 --- Two Second-order JB --- p.79 / Chapter 9 --- Conclusion --- p.81 / Chapter A --- Appendix --- p.83 / Chapter A.l --- Fourier Transform and Contour Integration --- p.83 / Chapter B --- Degeneracy and Criticality --- p.86 / Bibliography --- p.88

CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on "split ADC" architecture. Each of the two split channels, ADC "A" and "B", contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs' sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADC’s LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate).

Joseph C. Pitts, William F. Wicks [and] Edward E. David, Jr. / September 11, 1950." "Supplement of Technical report no.63." / Bibliography: p. 13. / Army Signal Corps Contract No. W36-039-sc-32037 Project No. 102B. Dept. of the Army Project No. 3-99-10-022.

E.E. David, Jr. / "This report is based on work contained in a Doctoral thesis in theDepartment of Electrical Engineering." "August 6, 1950." / Bibliography: p. 15. / Army Signal Corps Contract No. W36-039-sc-32037 Project No. 102B Dept. of the Army Project No. 3-99-10-022