This thesis demonstrates that the formation of titanium disilicide for gate level interconnects in silicon VLSI processes is possible, and is compatible with the processes considered. By using this new material the operating speed of fine geometry integrated circuits can be increased. The first two chapters consider the choice of titanium disilicide as a replacement for polysilicon. A process schedule is developed which enables the deposition and annealing of cosputtered films of titanium and silicon. By carefully controlling their deposition, cosputtered films have been annealed in both standard diffusion furnaces and also in rapid isothermal anneal (RIA) systems. This success in annealing titanium disilicide films in a RIA system is a world first. Next a process schedule for the deposition and anneal of titanium films over silicon is determined. The reaction of the film with the anneal ambient and the movement of impurities inevitably present in the titanium film is considered in some detail. This work was the first to highlight the benefits gained from the use of nitrogen as the anneal ambient. Self-aligned processes rely on the interaction between titanium and silicon dioxide being negligible. The silicide formation anneal is therefore optimised to minimise this. Finally, reaction of the silicide with common dopants and with both oxidising and nitriding ambients is presented. A novel method of forming a titanium nitride over silicide contact structure is developed. In summary, this thesis demonstrates how a titanium disilicide based metallisation can be implemented into an existing MOS process.

The MOS device is the basic switching element in modern integrated circuits, and its reliability is vital to the successful operation of electronic equipment. Exposure to ionising radiation seriously affects MOS devices because of charge trapping and the formation of defects at the silicon-silicon dioxide interface. After an introductory chapter on MOS devices and radiation effects, experiments are described which give information about the nature of the interface defects and how they interact with each other. A particular device current Irec is measured whose magnitude depends on the recombination of charge carriers at the defects. The device is so minute, and the interface so thin, that the paramagnetic defects are too few in number to be detected and identified by conventional electron spin resonance methods. However, the static and microwave magnetic fields corresponding to spin resonance affect the recombination of carriers on the defects, and this causes a detectable change in Irec. This phenomenon is called Spin-Dependent Recombination (SOR), and a survey of SOR studies in semiconductors is given in Chapter 2 . The experimental results confirm a model which suggests that SOR occurs between adjacent trapped pairs. The results of the experiments are compared with ESR data on similar (but much larger) MOS structures. Spin-Dependent Generation of carriers is also investigated. The recombination is also found to be strongly dependent on a static magnetic field of zero to 5 milliTesla, even with no microwaves. Results of experiments on these "non-resonant" spin-dependent effects are presented with a model, relating them to the resonance experiments, which involves the recombination of singlet and triplet electron-hole pairs in a magnetic field. Electrical charge injection can affect MOS devices in similar ways to ionising radiation, and this is discussed in Chapter 6. Experimental results are presented which show that there are spin-dependent effects associated with defects produced by electrical charge injection. There are two Appendices, on slow radiation-induced instabilities in MOS structures, and on the size of the recombination current Irec�

published_or_final_version / Electrical Engineering / Doctoral / Doctor of Philosophy

No description available.

The dependence of the substrate resistance, R[subscript sub], for MOS transistor RF modeling on transistor biasing and layout is studied from device simulations and measurements. Though R[subscript sub] is found to be bias dependent, the error incurred by assuming a constant value equal to the DC resistance is not significant. A scalable model for R[subscript sub] of multiple gate fingers is developed. This model is simple to extract and gives good agreement for the output admittance of a MOSFET. The model is validated by measurements on DC test structures fabricated in a TSMC 0.35 ��m CMOS process. The dependence of Rb on transistor dimensions and the location of substrate contacts with respect to device active area is also presented. A low noise amplifier (LNA) is designed and fabricated in the 0.35 ��m TSMC process to show the effect of R[subscript sub] on the performance of a LNA. / Graduation date: 2003

Thesis (Ph.D.)--Stanford University, 2006. / Adviser: Krishna C. Saraswat. Includes bibliographical references (p. 160-177)

Not available

Graduation date: 1990

Thesis (Ph. D.)--University of Texas at Austin, 2001. / Vita. Includes bibliographical references. Available also from UMI/Dissertation Abstracts International.

Thesis (Ph.D.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on Feb. 10, 2010). Bibliography: leaves 146-153.