Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographical references (p. 83-85).

A voltage controlled oscillator (VCO), that generates a periodic signal whose frequency is tuned by a voltage, is a key building block in any integrated circuit systems. A sine wave oscillator can be used for a built-in self testing where high linearity is required. A bandpass filter (BPF) based oscillator is a preferred solution, and high quality factor (Q-factor) is needed to improve the linearity. However, a stringent linearity specification may require very high Q-factor, not practical to implement. To address this problem, a frequency harmonic shaping technique is proposed. It utilizes a finite impulse response filter improving the linearity by rejecting certain harmonics. A prototype SC BPF oscillator with an oscillating frequency of 10 MHz is designed and measurement results show that linearity is improved by 20 dB over a conventional oscillator. In radio frequency area, preferred oscillator structures are an LC oscillator and a ring oscillator. An LC oscillator exhibits good phase noise but an expensive cost of an inductor is disadvantageous. A ring oscillator can be built in standard CMOS process, but suffers due to a poor phase noise and is sensitive to supply noise. A RC BPF oscillator is proposed to compromise the above difficulties. A RC BPF oscillator at 2.5 GHz is designed and measured performance is better than ring oscillators when compared using a figure of merit. In particular, the frequency tuning range of the proposed oscillator is superior to the ring oscillator. VCO is normally incorporated with a frequency synthesizer (FS) for an accurate frequency control. In an integer-N FS, reference spur is one of the design concerns in communication systems since it degrades a signal to noise ratio. Reference spurs can be rejected more by either the lower loop bandwidth or the higher loop filter. But the former increases a settling time and the latter decreases phase margin. An adaptive lowpass filtering technique is proposed. The loop filter order is adaptively increased after the loop is locked. A 5.8 GHz integer-N FS is designed and measurement results show that reference spur rejection is improved by 20 dB over a conventional FS without degrading the settling time. A new pulse interleaving technique is proposed and several design modifications are suggested as a future work.

No description available.

Thesis (Ph. D.)--Washington State University, August 2008. / Includes bibliographical references (p. 84-85).

Note:

Phase locked loops (PLLs) used to generate high precision clocks are integral components in the majority of modern day electronic systems such as Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), transceivers, processors, etc. The accuracy of this clocks that effects the overall performance of the system is measured in terms of its jitter, phase noise, spurious tones, etc. For example, the jitter in an ADC sampling clock can result in uncertainty of the sampling instant and can result in degradation of the effective number of bits (ENOB) of the ADC, phase noise on the other hand can result in reciprocal mixing in receivers and leakage into adjacent channels in transmitters. Therefore it is very desirable to design PLLs that generate clean clocks with minimal area and power consumption. This thesis discusses two PLL prototypes in 65nm CMOS technology. The first prototype demonstrates a sub-sampling phase detector (SSPD) based feed-forward noise cancellation (FFNC) scheme in a Type-II ring oscillator (RO) PLL. The FFNC technique uses the already available noise information at the SSPD output and cancels it from the PLL output. The proposed FFNC achieves a 1.4x reduction in jitter, 19.5dB power supply induced noise suppression at the PLL output while consuming a small area of 0.022mm2. The second prototype demonstrates a Type-I SSPD based RO PLL. The SSPD sample-and-hold action generates a steady-state voltage to tune the VCO directly. This eliminates the issue of high reference spurs generally associated with a Type-I PLL. Also the Type-I PLL occupies a very low area of 0.008mm2 as it avoids the usage of bulky integrating capacitor generally used in a Type-II PLL. The PLL with 2.4GHz output achieves a phase noise of -122.6dBc/Hz at a 1MHz offset and the power consumption is 6.1mW. It achieves reference spurs of -64.2dBc, RMSjitter of 422fs and FoMjitter of -239.7dB. In addition to the two prototypes, a theoretical discussion on an auxiliary FFNC (AFFNC) cancellation scheme that can work with a generic Type-II RO PLL is also included. The AFFNC technique uses a stand alone SSPD to extract and cancel noise from the VCO output. The SSPD is embedded into an alignment loop for proper noise extraction and cancellation. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also included. By using both the reference edges, higher cancellation BW is achieved.

The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage, the design also possesses another feature, i.e., fast locked time. The second topic is the half-swing PLA circuit. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. The third topic is a novel design of a the 1.0 GHz pipelining 8-bit CLA based on the architecture we mentioned in the second topic. The operating clock frequency is 1.0 GHz and the output of the addition of two 8-bit binary numbers is done in 2 cycles ( 2.0 ns ).

As an increasing number of distributed power generation systems (DPGS) are being connected to the utility grid, there is a growing requirement for the DPGS to be able to ride through short grid disturbances. This requires improvements to be made to the grid-side control scheme of the DPGS. An important part of the grid-side control scheme is the grid synchronization method, which is responsible for tracking the phase angle of the grid voltage vector. The state-of-the-art grid synchronization methods being used today are phase-locked loops. This thesis presents a modified phase-locked loop which is more robust towards grid disturbances. It consists of a multi-block adaptive notch filter (ANF) integrated into a conventional three-phase synchronous reference frame phase-locked loop (SRF-PLL). The addition of the multi-block ANF to the system allows it to become frequency adaptive. Also, since the multi-block ANF consists of multiple ANF blocks in parallel with one another, the system is able to remove multiple input signal distortions. Thus, the proposed system is able to eliminate the double frequency ripple that is caused in the conventional three-phase SRF-PLL by input unbalance, as well as harmonic errors, despite the presence of frequency variations in the input signal. Simulation results found using Matlab/Simulink, and experimental results found using the dSPACE DS1103 DSP board, demonstrate the feasibility of the modified SRF-PLL. Also, the modified SRF-PLL is compared to a conventional three-phase SRF-PLL, as well as to a conventional three-phase SRF-PLL with a simple notch filter, and the advantages of the modified SRF-PLL are discussed. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-12-17 12:38:02.589

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Thesis (M.S.)--Oregon State University, 2009. / Printout. Includes bibliographical references (leaves 43-45). Also available on the World Wide Web.