Global ETD Search

11	Ein generisches Konzept zur Modellierung und Bewertung feldprogrammierbarer Architekturen Wolz, Frank. January 2004 (has links) (PDF) Würzburg, Univ., Diss., 2004. / Erscheinungsjahr auf Titelseite: 2003. Field programmable gate array
12	Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping / Sedaghat Maman, Reza. January 1999 (has links) (PDF) Hannover, University, Diss., 1999. Field programmable gate array
13	Ein generisches Konzept zur Modellierung und Bewertung feldprogrammierbarer Architekturen Wolz, Frank. January 2004 (has links) (PDF) Würzburg, Universiẗat, Diss., 2004. / Erscheinungsjahr an der Haupttitelstelle: 2003. Field programmable gate array
14	Das FPGA-Entwicklungssystem CHDL eine vollständige, C++-basierte Entwicklungsumgebung für FPGA-Koprozessoren / Kornmesser, Klaus. January 2004 (has links) (PDF) Mannheim, Universiẗat, Diss., 2004. Field programmable gate array
15	Single event upset testing of flash based field programmable gate arrays Potgieter, Juan-Pierre January 2015 (has links) In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities; all this has made circuits more sensitive to various kinds of failures. These trends allowed soft errors, which up until recently was just a concern for space application, to become a major source of system failures of electronic products. The aim of this research paper was to investigate different mitigation techniques that prevent these soft errors in a Video Graphics Array (VGA) controller which is commonly used in projecting images captured by cameras. This controller was implemented on a Flash Based Field Programmable Gate array (FPGA). A test set-up was designed and implemented at NRF iThemba LABS, which was used to conduct the experiments necessary to evaluate the effectiveness of different mitigation techniques. The set-up was capable of handling multiple Device Under Tests (DUT) and had the ability to change the angle of incidence of each DUT. The DUTs were radiated with a 66MeV proton beam while the monitoring equipment observed any errors that had occurred. The results obtained indicated that all the implemented mitigation techniques tested on the VGA system improved the system’s capability of mitigating Single Event Upsets (SEU). The most effective mitigation technique was the OR-AND Multiplexer Single Event Transient (SET) filter technique. It was thus shown that mitigation techniques are viable options to prevent SEU in a VGA controller. The permanent SEU testing set-up which was designed and manufactured and was used to conduct the experiments, proved to be a practical option for further microelectronics testing at iThemba LABS. Field programmable gate arrays
16	Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays Newalkar, Aditya, January 2005 (has links) (PDF) Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.
17	Design of an FPGA based parallel architecture processor for displaying CSG volumes and surfaces Cevik, Ulus January 1996 (has links) No description available. 621.3994 Field programmable gate array
18	Genetic programming in hardware Martin, Peter N. January 2003 (has links) No description available. 006 Field programmable gate array
19	Dynamically reconfigurable intellectual property cores MacBeth, John Stuart January 2003 (has links) No description available. 621 Field programmable gate array
20	Design and implementation of a high level image processing machine using reconfigurable hardware Donachy, Paul January 1996 (has links) No description available. 621.3994 Field Programmable Gate Array

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