RAID-6 is widely used to tolerate concurrent failures of any two disks to provide a higher level of reliability with the support of erasure codes. Among many implementations, one class of codes called Maximum Distance Separable (MDS) codes aims to offer data protection against disk failures with optimal storage efficiency. Typical MDS codes contain horizontal and vertical codes. However, because of the limitation of horizontal parity or diagonal/anti-diagonal parities used in MDS codes, existing RAID-6 systems suffer several important problems on performance and scalability, such as low write performance, unbalanced I/O, and high migration cost in the scaling process. To address these problems, in this dissertation, we design techniques for high performance and scalable RAID-6 systems. It includes high performance and load balancing erasure codes (H-Code and HDP Code), and Stripe-based Data Migration (SDM) scheme. We also propose a flexible MDS Scaling Framework (MDS-Frame), which can integrate H-Code, HDP Code and SDM scheme together. Detailed evaluation results are also given in this dissertation.

RAID-6 is a data encoding scheme used to provide single drive error detection and dual drive error correction for data redundancy on an array of disks. Here we present a thorough study of efficient implementations of RAID-6 on field programmable gate arrays (FPGAs). Since RAID-6 relies heavily on Galois Field Algebra (GFA), an efficient implementation of a GFA FPGA library is also presented. Through rigorous performance analysis, this work shows the most efficient ways to tradeoff FPGA resources and execution time when implementing GFA functions as well as RAID-6 encoding and decoding.