Thesis submitted in partial fulfilment of the requirements for the degree Master of Technology: Electrical Engineering in the Faculty of Engineering at the Cape Peninsula University of Technology 2015 / Space-borne GPS receivers designed for nano-satellites are faced with various challenges. This research is undertaken to address the problems of inefficiency and high-costs associated with space-borne GPS receivers. The problem of inefficiency relates to poor performances of the GPS receiver in terms of the algorithmic models, execution speed, memory usage and errors proness. The problem of high-costs relates to the spacegrade hardware cost, implementation complexity, development time, as well as the manufacturing, production and the testing processes involved. The research objectives are to i) establish an efficient high-dynamics software-defined GPS receiver, ii) demonstrate a firmware approach and then iii) postulate a low-cost hardware implementation roadmap. The research methodology employed to address the problems and to attain the objectives is based-on using Matlab computing platform to i) implement a software-defined GPS receiver using free open-source GPS receiver algorithms, ii) further develop the software GPS receiver and lastly iii) convert the improved GPS receiver algorithms to firmware. The GPS receiver was successfully implemented in Matlab floating-point algorithms with a ±100kHz Doppler search bins and was used to post-process a pre-captured real GPS L1 C/A signal dataset. The pre-captured GPS signal was acquired, tracked, decoded and post-processed to extract the navigation message; use to compute the GPS receiver position, UTC date and time. Attempt to convert the entire Matlab floating-point GPS receiver algorithms to equivalent VHDL implementations failed; however, three of the Matlab floating-point algorithms (check_t.m, deg2dms.m and findUtmZone.m), were successfully converted to equivalent fixed-point formats in Matlab, Simulink and finally VHDL. These three algorithms, now created and optimised to fixed-point formats (efficient and enable implementation unto a low-cost microcontroller), set the basis for the firmware implementation. They were simulated and verified in Matlab, Simulink and VHDL using the Matlab HDL Coder workflow. Altera Quartus II software was then used to compile (synthesise, place & route and generate programming files) the three converted generic VHDL algorithms to embedded firmware, suitable for a FPGA programming. The Matlab HDL Coder workflow used in this research is feasible and can be used to accurately design and implement an improved GPS receiver and furthermore achieve it in three equivalent algorithms. This conclusion was drawn and the proposed recommendations are to address the conversion issues in the other Matlab floating-point GPS receiver algorithms that failed in the conversion process and to further develop and implement the GPS receiver as a fully functional unit, based-on the Xilinx space-grade, radiation hardened and low-cost Virtex 5QV FPGA.

The determination of the optimal location of transceivers is a critical design factor when deploying a wireless local area network (WLAN). The performance of the WLAN will improve in a variety of aspects when the transceivers' locations are adequately determined, including the overall cell coverage to the battery life of the client units. Currently, the most common method to determine the appropriate location of transceivers is known as a site survey, which is normally a very time and energy consuming process. The main objective of this research was to improve current methodologies for the optimal or near-optimal placement of APs in a WLAN installation. To achieve this objective, several improvements and additions were made to an existing computational tool to reflect the evolution that WLAN equipment has experienced in recent years. Major additions to the computational tool included the addition of the capability to handle multiple power levels for the transceivers, the implementation of a more adequate and precise representation of the passive interference sources for the path loss calculations, and the definition of a termination criterion to achieve reasonable computational times without compromising the quality of the solution. An experiment was designed to assess how the improvements made to the computational tool provided the desired balance between computational time and the quality of the solutions obtained. The controlled factors were the level of strictness of the termination criterion (i.e., high or low), and the number of runs performed (i.e., 1, 5, 10, 15, and 20 runs). The low level of strictness proved to dramatically reduce (i.e., from 65 to 70%) the running time required to obtain an acceptable solution when compared to that obtained at the high level of strictness. The quality of the solutions found with a single run was considerably lower than that obtained with the any other number of runs. On the other hand, the quality of the solutions seemed to stabilize at and after 10 runs, indicating that there is no added value to the quality of the solution when 15 or 20 runs are performed. In summary, having the computational tool developed in this research execute 5 runs with the low level of strictness would generate high quality solutions in a reasonable running time. / Graduation date: 2004

In downlink multi-user multiple-input multiple-output (MU-MIMO) systems, different users, even multiple data streams serving one user, might require different quality-of-services (QoS). The transceiver should allocate resources to different users aiming at satisfying their QoS requirements. In order to design the optimal transceiver, channel state information is necessary. In practice, channel state information has to to be estimated, and estimation error is unavoidable. Therefore, robust transceiver design, which takes the channel estimation uncertainty into consideration, is important. For the previous robust transceiver designs, bounded estimation errors or Gaussian estimation errors were assumed. However, if there exists unknown distributed interference, the distribution of the channel estimation error cannot be modeled accurately a priori. Therefore, in this thesis, we investigate the robust transceiver design problem in downlink MU-MIMO system under probabilistic QoS constraints with arbitrary distributed channel estimation error. To tackle the probabilistic QoS constraints under arbitrary distributed channel estimation error, the transceiver design problem is expressed in terms of worst-case probabilistic constraints. Two methods are then proposed to solve the worst-case problem. Firstly, the Chebyshev inequality based method is proposed. After the worst-case probabilistic constraint is approximated by the Chebyshev inequality, an iteration between two convex subproblems is proposed to solve the approximated problem. The convergence of the iterative method is proved, the implementation issues and the computational complexity are discussed. Secondly, in order to solve the worst-case probabilistic constraint more accurately, a novel duality method is proposed. After a series of reformulations based on duality and S-Lemma, the worst-case statistically constrained problem is transformed into a deterministic finite constrained problem, with strong duality guaranteed. The resulting problem is then solved by a convergence-guaranteed iteration between two subproblems. Although one of the subproblems is still nonconvex, it can be solved by a tight semidefinite relaxation (SDR). Simulation results show that, compared to the non-robust method, the QoS requirement is satisfied by both proposed algorithms. Furthermore, among the two proposed methods, the duality method shows a superior performance in transmit power, while the Chebyshev method demonstrates a lower computational complexity. / published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Hon Kwok-Wai. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 89-91). / Abstracts in English and Chinese. / Chapter 1. --- System Architecture --- p.1 / Chapter 1.1 --- Introduction --- p.1 / Chapter 1.2 --- Receiver Architectures --- p.2 / Chapter 1.2.1 --- Superheterodyne Receiver --- p.2 / Chapter 1.2.2 --- Homodyne Receiver --- p.3 / Chapter 1.2.3 --- Image-Reject Receiver --- p.5 / Chapter 1.2.4 --- Low intermediate frequency Receiver --- p.7 / Chapter 1.3 --- Double Intermediate Frequency Receivers --- p.8 / Chapter 1.3.1 --- Introduction --- p.8 / Chapter 1.3.2 --- Background Theory --- p.8 / Chapter 2. --- Receiver Fundamentals --- p.23 / Chapter 2.1 --- Noise model --- p.23 / Chapter 2.1.1 --- Thermal noise of resistors --- p.23 / Chapter 2.1.2 --- Channel noise of transistors --- p.24 / Chapter 2.2 --- Noise Figure --- p.26 / Chapter 2.3 --- Linearity --- p.26 / Chapter 2.3.1 --- 1 -dB Compression point --- p.27 / Chapter 2.3.2 --- Third Intercept point (IP3) --- p.28 / Chapter 2.3.3 --- Dynamic Range (DR) --- p.30 / Chapter 2.3.3.1 --- Spurious-Free Dynamic Range (SFDR) --- p.30 / Chapter 2.3.3.2 --- Blocking Dynamic Range (BDR) --- p.32 / Chapter 3. --- Spiral Inductor --- p.33 / Chapter 3.1 --- Spiral inductor modeling --- p.34 / Chapter 3.2 --- Spiral Inductor model parameters --- p.36 / Chapter 3.3 --- Characteristic of spiral inductor --- p.36 / Chapter 3.4 --- Inductor Design and Optimization --- p.37 / Chapter 4. --- Low Noise Amplifier (LNA) --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Common LNA Architectures --- p.39 / Chapter 4.2.1 --- Resistive Termination --- p.39 / Chapter 4.2.2 --- 1/gm Termination --- p.42 / Chapter 4.2.3 --- Shunt-Series Feedback --- p.43 / Chapter 4.2.4 --- Inductive Source Degeneration --- p.43 / Chapter 4.3 --- Full Schematic diagram of the Low Noise Amplifier --- p.45 / Chapter 4.4 --- Full noise analysis of the LNA using inductive source degeneration --- p.46 / Chapter 4.4.1 --- Output noise due to channel noise --- p.46 / Chapter 4.4.1.1 --- Output noise due to i2d --- p.47 / Chapter 4.4.1.2 --- "Output noise due to i2g,u" --- p.47 / Chapter 4.4.1.3 --- "Output noise due to i2g,c and i2d" --- p.49 / Chapter 4.4.2 --- "Output noise due to Rg R,l Rs" --- p.51 / Chapter 4.4.3 --- Noise factor calculation --- p.52 / Chapter 4.4.3.1 --- Rl calculation --- p.52 / Chapter 4.4.3.2 --- Rg calculation --- p.52 / Chapter 4.4.3.3 --- Ql calculation --- p.53 / Chapter 4.4.3.4 --- wT calculation --- p.53 / Chapter 4.4.3.5 --- x calculation --- p.53 / Chapter 4.5 --- Simulation Result of the low noise amplifier (100 finger gate poly) --- p.54 / Chapter 4.5 --- Experimental Result of the low noise amplifier (100 finger gate poly) --- p.56 / Chapter 5. --- Down-conversion Mixer --- p.58 / Chapter 5.1 --- Introduction --- p.58 / Chapter 5.2 --- Gilbert Cell Mixer --- p.59 / Chapter 5.2.1 --- Circuit Description --- p.59 / Chapter 5.2.2 --- Basic Operation --- p.60 / Chapter 5.2.3 --- Simulation Result of the Gilbert Cell Mixer --- p.62 / Chapter 5.3 --- Single-ended to Differential-ended Converter --- p.66 / Chapter 5.3.1 --- Simulation Result of the Single-Ended to Differential-Ended Converter --- p.68 / Chapter 5.4 --- Experimental Result of The Gilbert Cell Mixer --- p.70 / Chapter 5.4.1 --- 1-dB compression point experiment --- p.70 / Chapter 5.4.2 --- IIP3 experimental setup and result --- p.72 / Chapter 5.4.3 --- "Experimental result of 1 -dB compression point, IIP3, conversion gain, SFDR and BDR" --- p.74 / Chapter 5.4.4 --- LO power verse conversion gain --- p.75 / Chapter 5.4.5 --- Intermediate frequency verse conversion gain --- p.77 / Chapter 5.4.6 --- Experimental result of input matching and isolation --- p.78 / Chapter 6. --- Asymmetric Polyphase Network --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Performance of the Asymmetric Polyphase Network --- p.81 / Chapter 6.2.1 --- First Building Block --- p.82 / Chapter 6.2.2 --- Second Building Block --- p.83 / Chapter 6.2.3 --- Third Building Block --- p.84 / Chapter 6.2.4 --- Forth Building Block --- p.84 / Chapter 6.3 --- Simulation result of the asymmetric polyphase network --- p.85 / Chapter 6.4 --- Experimental result of the asymmetric polyphase network --- p.86 / Chapter 7. --- Conclusion --- p.87 / Chapter 8. --- Reference --- p.89 / Chapter 9. --- Appendix A --- p.92 / Chapter 10. --- Appendix B --- p.95 / Chapter 11. --- Appendix C --- p.98 / Chapter 12. --- Appendix D --- p.99

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Not available / text

Time Average Fourier Telescopy (TAFT) has been proposed as a means for obtaining high-resolution, diffraction-limited images over large distances through ground-level horizontal-path atmospheric turbulence. Image data is collected in the spatial-frequency, or Fourier, domain by means of Fourier Telescopy; an inverse two dimensional Fourier transform yields the actual image. TAFT requires active illumination of the distant object by moving interference fringe patterns. Light reflected from the object is collected by a “light-bucket” detector, and the resulting electrical signal is digitized and subjected to a series of signal processing operations, including an all-critical averaging of the amplitude and phase of a number of narrow-band signals. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2014. / FAU Electronic Theses and Dissertations Collection

This paper introduces a component of the Radio Frequency transceiver called the mixer. The mixer is a critical component in the RF systems, because of its ability for frequency conversion. This passage focuses on the design analysis and simulation of multiple topologies for the active down-conversion mixer. This mixer is characterized by its important design properties which consist of conversion gain, linearity, noise figure, and port isolation. The topologies that are given in this passage range from the most commonly known mixer design, to implemented design techniques that are used to increase the mixers important design properties as the demand of CMOS technology and the overall RF system rises. All mixer topologies were designed and simulated using TSMC 0.18 µm CMOS technology in Advanced Design Systems, a simulator used specifically for RF designs.