Integrating nanometer-sized pores into low-k ILD films is one of the approaches to lower the RC signal delay and thus help sustain the continued scaling of microelectronic devices. While increasing porosity of porous dielectrics lowers the dielectric constant (k), it also creates many reliability and implementation issues. One of the problems is the little understood metal ion diffusion and drift in porous media. Here, we present a rigorous simulation method of Cu diffusion based on Master equation with elementary jump probabilities within the contiguous dielectric film, along the pore boundary, from the dielectric matrix to the pore boundary, and from the pore boundary to the matrix material. In view of the diffusional jump distance being as large as 2 nm, the nano-pores being on a similar length scale, and the film thickness being only a few tens of nanometers, the conventional diffusion equation in differential equation form is grossly inadequate and elementary jump frequencies are required for a proper description of the Cu diffusion in porous dielectric. The present atomistic approach allows a consistent implementation of Cu ion drift in electric field by lowering and raising of the diffusion barriers along the field direction. This will help understand the behavior of Cu interconnects under thermal or electric stress at an atomistic level. Another approach to lower the increasing RC delays is to bring memory and logic closer by integrating memory in the BEOL. Resistive RAM is one such memory is not transistor based and thus, does not require a silicon substrate. Thus, it offers the possibility of integration directly into the back-end reducing memory to logic distance from 1000s of µm to a 10s of nm. This 3D integration also allows for increased density as well. However, one barrier in the implementation of RRAM in the back end is the use of expensive as well as non-BEOL native material in conventional Cu/TaOx/Pt resistive devices. In this thesis, we present our research about functionality of RRAM with porous low-k dielectrics (which are a candidate for CMOS ILD), and through the similar elementary jump simulations, discuss the impact of porosity in dielectrics on the functionality of RRAM. Lastly, we present a cheaper replacement for Pt as the counter electrode in RRAM and show that it functions as good as Pt. This work addresses following three areas: 1. Modeling of diffusion in porous dielectrics through elementary jump based simulation. The model is based on random walk theory of elementary particle jumps. Initially, qualitative simulations are conducted without actual parameters. It is shown that Cu diffusion in porous dielectrics decreases quasi-linearly with porosity. Furthermore, it is shown that morphology of the pores may have a greater effect on diffusivity compared to porosity. The simulations are then calibrated with parameters, and the result is shown to yield a similar diffusivity times as actual process time. 2. Modeling of Cu ions drift in porous dielectrics under electric stress. First, the model is explained, and then qualitative simulation results are presented for porous dielectrics with varied porosities and morphologies. 3. Research to find a suitable replacement for Pt as the counter electrode in RRAM devices. The research methodology is discussed and a much cheaper Rh is selected as the potential replacement for Pt. Successful functionality of Rh based resistive devices is presented. / Master of Science / As electronic devices are being scaled for integrating more functions and higher computation, the internal delays are increasing, which may become a bottleneck in performance. To resolve this issue of internal delay, new materials are being proposed to replace the conventional materials to make the chip. One promising material like that are the porous dielectrics, to replace the conventional dielectrics used to manufacture electronic chips. The introduction of ‘air pores’ inside the dielectric used in chips may improve the delay, but it leads to several thermal and electrical reliability concerns. In this thesis, we argue that using differential equations to simulate effects on the nano-scale to explore such reliability issues is insufficient, and a simulation method based on individual atom/ion movement should be used to describe it. Here we provide a simulation model to explain the diffusivity of copper under thermal stress, as well as movement of Cu ions during electric stress in porous dielectrics, using our particle movement based simulation model, and prove that it delivers correct results. Secondly, the delay is especially significant for processor to memory communication. Thus, integrating memory close to processor is another method to reduce the delay. Resistive RAM (RRAM) is one such novel RAM technology that can be integrated close to processor. However due to usage of non-native as well as expensive materials, RRAM has not been commercially integrated close to processor. In this thesis, we also present a functioning RRAM using cheaper materials, as well as materials that are native to present electronics.