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Scaling down of the CMOS technology requires thinner gate dielectric to maintain high performance. However, due to the depletion of poly-Si gate, it is difficult to reduce the gate thickness further especially for sub-65 nm CMOS generation. Fully silicidation metal gate (FUSI) is one of the most promising solutions. Furthermore, FUSI metal gate reduces gate-line sheet resistance, prevents boron penetration to channels, and has good process compatibility with high-k gate dielectric. Poly-SiGe gate technology is another solution because of its enhancement of boron activation and compatibility with the conventional CMOS process. Combination of these two technologies for the formation of fully germanosilicided metal gate makes the approach very attractive. In this paper, the deposition of undoped Poly-Si₁₋xGex (0 < x < 30% ) films onto SiO₂ in a low pressure chemical vapor deposition (LPCVD) system is described. Detailed growth conditions and the characterization of the grown films are presented. / Singapore-MIT Alliance (SMA)

Applications of semiconductor nanocrystal in electronics are promising. Various techniques were developed to synthesize and analyze semiconductor nanocrystals for integrated circuit applications. In this study, silicon and germanium nanocrystals were synthesized in silicon dioxide matrix by magnetron sputtering deposition and following high temperature furnace annealing. Multilayer and single layer samples were prepared by co-sputtering depositions. Transmission electron microscopy measurements were carried out to analyze annealing effects on nanocrystal size distribution, change in shape, density and localization in silicon dioxide (SiO2). Ge-Ge Traverse Optical (TO) peak was monitored using Raman spectroscopy to investigate germanium nanocrystal formation and stress effects of silicon dioxide. Si-O-Si asymmetric stretching band is examined by Fourier transform infrared transmission spectroscopy to study silicon dioxide matrix recovery with germanium nanocrystal formation. Luminescence characteristics of silicon nanocrystals in visible and near infrared region (550nm-1050nm) with changing nanocrystal size and density were studied with photoluminescence spectroscopy.

This thesis proposes a modified inductively degenerated common-emitter low-noise amplifier. To add a series-shunt feedback capacitance in series to the base of the cascode transistor for increasing the load impedance of the common-emitter transistor and enhancing the Miller effect, it is applied to improve the circuit¡¦s performance. By thoroughly studying the Miller effect for the input matching, noise, and linearity analysis and derivation of the modified structure, the theoretical analysis and experiments demonstrate the improved linearity and well noise performance. In addition, the proposed method is presented with the good figure of merit. The proposed method is presented in a hybrid circuit with the NEC 2S5010 NPN transistor for 900 MHz applications. It demonstrates that this method improves the linearity and the figure of merit has been increased by 50 to 70 percent. Moreover, the novel low noise amplifier is designed with a 0.35£gm SiGe BiCMOS process supported by the TSMC for 5.7 GHz WLAN band applications. It is found that the circuit has the characteristic of IM3 nonlinearity cancellation because the cascode transistor eliminates the third-order intermodulation genaerated by the common-emitter transistor. This thesis establishes a realizable method for high-linearity low-noise amplifier.