Multiple-input multiple-output (MIMO) technique in communication system has been widely researched. Compared with single-input single-output (SISO) communication, its properties of higher throughput, more e?cient spectrum and usage make it one of the most significant technology in modern wireless communications. In MIMO system, sphere detection is the fundamental part. The purpose of traditional sphere detection is to achieve the maximum likelihood (ML) demodulation of the MIMO system. However, with the development of advanced forward error correction (FEC) techniques, such as the Convolutional code, Turbo code and LDPC code, the sphere detection algorithms that can provide soft information for the outer decoder attract more interests recently. Considering the computing complexity of generating the soft information, it is important to develop a high-speed VLSI architecture for MIMO detection. The first part of this thesis is about MIMO sphere detection algorithms. Two sphere detection algorithms are introduced. The depth first Schnorr-Euchner (SE) algorithm which generates the ML detection solution and the width first K-BEST algorithm which only generates the nearly-ML detection solution but more efficient in implementation are presented. Based on these algorithms, an improved nearly-ML algorithm with lower complexity and limited performance lose, compared with traditional K-BEST algorithms, is presented. The second part is focused on the hardware design. A 4*4 16-QAM MIMO detection system which can generate both soft information and hard decision solution is designed and implemented in FPGA. With the fully pipelined and parallel structure, it can achieve a throughput of 3.7 Gbps. In this part, the improved nearly-ML algorithm is implmented as a detector to generat both the hard output and candidate list. Then, a soft information calculation block is designed to succeed the detector and produce the log-likelihood ratio (LLR) values for every bit as the soft output.

Powerful error-correcting codes have enabled a dramatic increase in the bit density on the recording medium of hard-disk drives (HDDs). Error-correcting codes in magnetic recording require a low-complexity decoder and a code design that delivers a target error-rate performance. This dissertation proposes an error-correcting system based on polar codes incorporating a fast, low-complexity, soft-output decoder and a design that is optimized for error-rate performance in the magnetic recording channel. LDPC codes are the state-of-the-art in HDDs, providing the required error-rate performance on high densities at the cost of increased computational complexity of the decoder. Substantial research in LDPC codes has focused on reducing decoder complexity and has resulted in many variants such as quasi-cyclic and convolutional LDPC codes. Polar codes are a recent and important breakthrough in coding theory, as they achieve capacity on a wide spectrum of channels using a low-complexity successive cancellation decoder. Polar codes make a strong case for magnetic recording, because they have low complexity decoders and adequate finite-length error-rate performance. In their current form, polar codes are not feasible for magnetic recording for two reasons. Firstly, there is no low-complexity soft-output decoder available for polar codes that is required for turbo-based equalization of the magnetic recording channel. The only soft-output decoder available to date is a message passing based belief propagation decoder that has very high computational complexity and is not suitable for practical implementations. Secondly, current polar codes are optimized for the AWGN channel only, and may not perform well under turbo-based detector for ISI channels. This thesis delivers a powerful low-complexity error-correcting system based on polar codes for ISI channels. Specifically, we propose a low-complexity soft-output decoder for polar codes that achieves better error-rate performance than the belief propagation decoder for polar codes while drastically reducing the complexity. We further propose a technique for polar code design over ISI channels that outperform codes for the AWGN channel in terms of error rate under the proposed soft-output decoder.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

In spread spectrum systems employing parity bit selected spreading sequences, parity bits generated from a linear block encoder are used to select a spreading code from a set of mutually orthogonal spreading sequences. In this thesis, turbo receivers for SS-PB systems are proposed and investigated. In the transmitter, data bits are rst convolutionally encoded before being fed into SS-PB modulator. In fact, the parity bit spreading code selection technique acts as an inner encoder in this system without allocating any transmit energy to the additional redundancy provided by this technique. The receiver implements a turbo processing by iteratively exchanging the soft information on coded bits between a SISO detector and a SISO decoder. In this system, detection is performed by incorporating the extrinsic information provided by the decoder in the last iteration into the received signal to calculate the likelihood of each detected bit in terms of LLR which is used as the input for a SISO decoder. In addition, SISO detectors are proposed for MC-CDMA and MIMO-CDMA systems that employ parity bit selected and permutation spreading. In the case of multiuser scenario, a turbo SISO multiuser detector is introduced for SS-PB systems for both synchronous and asynchronous channels. In such systems, MAI is estimated from the extrinsic information provided by the SISO channel decoder in the previous iteration. SISO multiuser detectors are also proposed for the case of multiple users in MC-CDMA and MIMO-CDMA systems when parity bit selected and permutation spreading are used. Simulations performed for all the proposed turbo receivers show a signi cant reduction in BER in AWGN and fading channels over multiple iterations.

A high-throughput low-power Soft-Output Viterbi decoder designed for the convolutional codes used in the ECMA-368 UWB standard is presented in this thesis. The ultra wide band (UWB) wireless communication technology is supposed to be used in physical layer of the wireless personal area network (WPAN) and next generation Blue Tooth. MB-OFDM is a very popular scheme to implement the UWB system and is adopted as the ECMA-368 standard. To make the high speed data transferred over the channel reappear reliably at the receiver, the error correcting codes (ECC) are wildly utilized in modern communication systems. The ECMA-368 standard uses concatenated convolutional codes and Reed-Solomon (RS) codes to encode the PLCP header and only convolutional codes to encode the PPDU Payload. The Viterbi algorithm (VA) is a popular method of decoding convolutional codes for its fairly low hardware implementation complexity and relatively good performance. Soft-Output Viterbi Algorithm (SOVA) proposed by J. Hagenauer in 1989 is a modified Viterbi Algorithm. A SOVA decoder can not only take in soft quantized samples but also provide soft outputs by estimating the reliability of the individual symbol decisions. These reliabilities can be provided to the subsequent decoder to improve the decoding performance of the concatenated decoder. The SOVA decoder is designed to decode the convolutional codes defined in the ECMA-368 standard. Its code rate and constraint length is R=1/3 and K=7 respectively. Additional code rates derived from the "mother" rate R=1/3 codes by employing "puncturing", including 1/2, 3/4, 5/8, can also be decoded. To speed up the add-compare-select unit (ACSU), which is always the speed bottleneck of the decoder, the modified CSA structure proposed by E.Yeo is adopted to replace the conventional ACS structure. Besides, the seven-level quantization instead of the traditional eight-level quantization is proposed to be used is in this decoder to speed up the ACSU in further and reduce its hardware implementation overhead. In the SOVA decoder, the delay line storing the path metric difference of every state contains the major portion of the overall required memory. A novel hybrid survivor path management architecture using the modified trace-forward method is proposed. It can reduce the overall required memory and achieve high throughput without consuming much power. In this thesis, we also give the way to optimize the other modules of the SOVA decoder. For example, the first K-1 necessary stages in the Path Comparison Unit (PCU) and Reliability Measurement Unit (RMU) are IX removed without affecting the decoding results. The attractiveness of SOVA decoder enables us to find a way to deliver its soft output to the RS decoder. We have to convert bit reliability into symbol reliability because the soft output of SOVA decoder is the bit-oriented while the reliability per byte is required by the RS decoder. But no optimum transformation strategy exists because the SOVA output is correlated. This thesis compare two kinds of the sub-optimum transformation strategy and proposes an easy to implement scheme to concatenate the SOVA decoder and RS decoder under various kinds of convolutional code rates. Simulation results show that, using this scheme, the concatenated SOVA-RS decoder can achieve about 0.35dB decoding performance gain compared to the conventional Viterbi-RS decoder.

The modeling of the soft-output decoding of a binary linear block code using a Binary Phase Shift Keying (BPSK) modulation system (with reduced noise power) is the main focus of this work. With this model, it is possible to provide bit error performance approximations to help in the evaluation of the performance of binary linear block codes. As well, the model can be used in the design of communications systems which require knowledge of the characteristics of the channel, such as combined source-channel coding. Assuming an Additive White Gaussian Noise channel model, soft-output Log Likelihood Ratio (LLR) values are modeled to be Gaussian distributed. The bit error performance for a binary linear code over an AWGN channel can then be approximated using the Q-function that is used for BPSK systems. Simulation results are presented which show that the actual bit error performance of the code is very well approximated by the LLR approximation, especially for low signal-to-noise ratios (SNR). A new measure of the coding gain achievable through the use of a code is introduced by comparing the LLR variance to that of an equivalently scaled BPSK system. Furthermore, arguments are presented which show that the approximation requires fewer samples than conventional simulation methods to obtain the same confidence in the bit error probability value. This translates into fewer computations and therefore, less time is needed to obtain performance results. Other work was completed that uses a discrete Fourier Transform technique to calculate the weight distribution of a linear code. The weight distribution of a code is defined by the number of codewords which have a certain number of ones in the codewords. For codeword lengths of small to moderate size, this method is faster and provides an easily implementable and methodical approach over other methods. This technique has the added advantage over other techniques of being able to methodically calculate the number of codewords of a particular Hamming weight instead of calculating the entire weight distribution of the code.

The modeling of the soft-output decoding of a binary linear block code using a Binary Phase Shift Keying (BPSK) modulation system (with reduced noise power) is the main focus of this work. With this model, it is possible to provide bit error performance approximations to help in the evaluation of the performance of binary linear block codes. As well, the model can be used in the design of communications systems which require knowledge of the characteristics of the channel, such as combined source-channel coding. Assuming an Additive White Gaussian Noise channel model, soft-output Log Likelihood Ratio (LLR) values are modeled to be Gaussian distributed. The bit error performance for a binary linear code over an AWGN channel can then be approximated using the Q-function that is used for BPSK systems. Simulation results are presented which show that the actual bit error performance of the code is very well approximated by the LLR approximation, especially for low signal-to-noise ratios (SNR). A new measure of the coding gain achievable through the use of a code is introduced by comparing the LLR variance to that of an equivalently scaled BPSK system. Furthermore, arguments are presented which show that the approximation requires fewer samples than conventional simulation methods to obtain the same confidence in the bit error probability value. This translates into fewer computations and therefore, less time is needed to obtain performance results. Other work was completed that uses a discrete Fourier Transform technique to calculate the weight distribution of a linear code. The weight distribution of a code is defined by the number of codewords which have a certain number of ones in the codewords. For codeword lengths of small to moderate size, this method is faster and provides an easily implementable and methodical approach over other methods. This technique has the added advantage over other techniques of being able to methodically calculate the number of codewords of a particular Hamming weight instead of calculating the entire weight distribution of the code.

Modern communication systems demand ever-increasing data rates. Meeting this increased demand is not easy due to regulation and fundamental physical constraints. The utilization of more than one antenna at both the transmitter and receiver produces a multiple-input multiple-output (MIMO) channel, thereby enabling (under certain channel conditions) increased data rates without the need for increased bandwidth or transmission power. Concurrent with this increase in bandwidth is an increase in the receiver's computational complexity which, for a brute-force detector, increases exponentially. For receivers that possess error correcting capabilities, the problem of constructing a detector with low computational complexity that allows for near-exact a posteriori detection is challenging for transmission schemes employing even a modest number of transmit antennas and modulation alphabet sizes. The focus of this dissertation is on the construction of MIMO detection algorithms with low and fixed computational complexity. Specifically, the detection algorithms in this dissertation generate a list of potential transmission vectors resulting in realizable communication receivers with low and fixed computational complexity combined with low error rate performance in both coded and uncoded systems. A key contribution in this dissertation is a breadth-first fixed-complexity algorithm known as the smart-ordered and candidate-adding algorithm that achieves a desirable performance-complexity tradeoff. This algorithm requires only a single pass of a search tree to find its list of transmission vectors. We then construct a framework within which we classify a large class of breadth-first detection algorithms. The design of receiver algorithms for MIMO systems employing space-time codes and error correction is an important area of study. In this dissertation we propose a low and fixed computational complexity algorithm for an increasingly significant algebraic space-time code known as the golden code. The notion of computational complexity is critical in the design of practical MIMO receivers. We provide an analysis of computational complexity in relation to list-based soft-output detection where, in some instances, bounds are placed on the computational complexity of MIMO detection. For this analysis we utilize a metric known as the number of branch metric computations. The value at which the log-likelihood ratio (LLR) of conditional probabilities for a transmitted bit being either a 1 or a 0 is 'clipped' has an impact on a system's error rate performance. We propose a new approach for determining LLR clipping levels that, in contrast to prior approaches which clip to a predetermined fixed LLR clipping level, exploits channel state information to improve the error rate performance of suboptimal detection algorithms. Orthogonal frequency-division (OFDM) multiplexing is an effective technique for combating frequency-selective wideband communication channels. It is common practice for MIMO-OFDM detectors to implement the same detector at each subcarrier, in which case the overall performance is dominated by the weakest subcarrier. We propose a hard-output list detection receiver strategy for MIMO-OFDM channels called nonuniform computational complexity allocation, whereby the receiver adapts the computational resources of the MIMO detector at each subcarrier to match a metric of the corresponding channel quality. The proposed nonuniform algorithm improves performance over uniform allocation.