Ce travail de thèse a pour cadre le projet Trusted Environment Execution eVAluation (TEEVA) (projet français FUI n°20 de Janvier 2016 à Décembre 2018) qui vise à évaluer deux solutions alternatives de sécurisation des plateformes mobiles, l’une est purement logicielle, la Whitebox Crypto, alors que l’autre intègre des éléments logiciels et matériels, le Trusted Environment Execution (TEE). Le TEE s’appuie sur la technologie TrustZone d’ARM disponible sur de nombreux chipsets du marché tels que des smartphones et tablettes Android. Cette thèse se concentre sur l’architecture TEE, l’objectif étant d’analyser les menaces potentielles liées aux infrastructures de test/debug classiquement intégrées dans les circuits pour contrôler la conformité fonctionnelle après fabrication.Le test est une étape indispensable dans la production d’un circuit intégré afin d’assurer fiabilité et qualité du produit final. En raison de l’extrême complexité des circuits intégrés actuels, les procédures de test ne peuvent pas reposer sur un simple contrôle des entrées primaires avec des patterns de test, puis sur l’observation des réponses de test produites sur les sorties primaires. Les infrastructures de test doivent être intégrées dans le matériel au moment du design, implémentant les techniques de Design-for-Testability (DfT). La technique DfT la plus commune est l’insertion de chaînes de scan. Les registres sont connectés en une ou plusieurs chaîne(s), appelé chaîne(s) de scan. Ainsi, un testeur peut contrôler et observer les états internes du circuit à travers les broches dédiées. Malheureusement, cette infrastructure de test peut aussi être utilisée pour extraire des informations sensibles stockées ou traitées dans le circuit, comme par exemple des données fortement corrélées à une clé secrète. Une attaque par scan consiste à récupérer la clé secrète d’un crypto-processeur grâce à l’observation de résultats partiellement encryptés.Des expérimentations ont été conduites sur la carte électronique de démonstration avec le TEE afin d’analyser sa sécurité contre une attaque par scan. Dans la carte électronique de démonstration, une contremesure est implémentée afin de protéger les données sensibles traitées et sauvegardées dans le TEE. Les accès de test sont déconnectés, protégeant contre les attaques exploitant les infrastructures de test, au dépend des possibilités de test, diagnostic et debug après mise en service du circuit. Les résultats d’expérience ont montré que les circuits intégrés basés sur la technologie TrustZone ont besoin d’implanter une contremesure qui protège les données extraites des chaînes de scan. Outre cette simple contremesure consistant à éviter l’accès aux chaînes de scan, des contremesures plus avancées ont été développées dans la littérature pour assurer la sécurité tout en préservant l’accès au test et au debug. Nous avons analysé un état de l’art des contremesures contre les attaques par scan. De cette étude, nous avons proposé une nouvelle contremesure qui préserve l’accès aux chaînes de scan tout en les protégeant, qui s’intègre facilement dans un système, et qui ne nécessite aucun redesign du circuit après insertion des chaînes de scan tout en préservant la testabilité du circuit. Notre solution est basée sur l’encryption du canal de test, elle assure la confidentialité des communications entre le circuit et le testeur tout en empêchant son utilisation par des utilisateurs non autorisés. Plusieurs architectures ont été étudiées, ce document rapporte également les avantages et les inconvénients des solutions envisagées en terme de sécurité et de performance. / This work is part of the Trusted Environment Execution eVAluation (TEEVA) project (French project FUI n°20 from January 2016 to December 2018) that aims to evaluate two alternative solutions for secure mobile platforms: a purely software one, the Whitebox Crypto, and a TEE solution, which integrates software and hardware components. The TEE relies on the ARM TrustZone technology available on many of the chipsets for the Android smartphones and tablets market. This thesis focuses on the TEE architecture. The goal is to analyze potential threats linked to the test/debug infrastructures classically embedded in hardware systems for functional conformity checking after manufacturing.Testing is a mandatory step in the integrated circuit production because it ensures the required quality and reliability of the devices. Because of the extreme complexity of nowadays integrated circuits, test procedures cannot rely on a simple control of primary inputs with test patterns, then observation of produced test responses on primary outputs. Test facilities must be embedded in the hardware at design time, implementing the so-called Design-for-Testability (DfT) techniques. The most popular DfT technique is the scan design. Thanks to this test-driven synthesis, registers are connected in one or several chain(s), the so-called scan chain(s). A tester can then control and observe the internal states of the circuit through dedicated scan pins and components. Unfortunately, this test infrastructure can also be used to extract sensitive information stored or processed in the chip, data strongly correlated to a secret key for instance. A scan attack consists in retrieving the secret key of a crypto-processor thanks to the observation of partially encrypted results.Experiments have been conducted during the project on the demonstrator board with the target TEE in order to analyze its security against a scan-based attack. In the demonstrator board, a countermeasure is implemented to ensure the security of the assets processed and saved in the TEE. The test accesses are disconnected preventing attacks exploiting test infrastructures but disabling the test interfaces for testing, diagnosis and debug purposes. The experimental results have shown that chips based on TrustZone technology need to implement a countermeasure to protect the data extracted from the scan chains. Besides the simple countermeasure consisting to avoid scan accesses, further countermeasures have been developed in the literature to ensure security while preserving test and debug facilities. State-of-the-art countermeasures against scan-based attacks have been analyzed. From this study, we investigate a new proposal in order to preserve the scan chain access while preventing attacks, and to provide a plug-and-play countermeasure that does not require any redesign of the scanned circuit while maintaining its testability. Our solution is based on the encryption of the test communication, it provides confidentiality of the communication between the circuit and the tester and prevents usage from unauthorized users. Several architectures have been investigated, this document also reports pros and cons of envisaged solutions in terms of security and performance.

Accurate transistor models are important in wireless and microwave circuit design. Large-signal field-effect transistor (FET) models are generally extracted from current-voltage (IV) characteristics, small-signal S-parameters, and large-signal measurements. This dissertation describes improved characterization and measurement validation techniques for FET models that correctly account for thermal and trapping effects. Demonstration of a customized pulsed-bias, pulsed-RF S-parameter system constructed by the author using a traditional vector network analyzer is presented, along with the design of special bias tees to allow pulsing of the bias voltages. Pulsed IV and pulsed-bias S-parameter measurements can provide results that are electrodynamically accurate; that is, thermal and trapping effects in the measurements are similar to those of radio-frequency or microwave operation at a desired quiescent bias point. The custom pulsed S-parameter system is benchmarked using passive devices and advantages and tradeoffs of pulsed S-parameter measurements are explored. Pulsed- and continuous-bias measurement results for a high-power transistor are used to validate thermal S-parameter correction procedures. A new implementation of the steepest-ascent search algorithm for load-pull is presented. This algorithm provides for high-resolution determination of the maximum power and associated load impedance using a small number of measured or simulated reflection-coefficient states. To perform a more thorough nonlinear model validation, it is often desired to find the impedance providing maximum output power or efficiency over variations of a parameter such as drain voltage, input power, or process variation. The new algorithm enables this type of validation that is otherwise extremely tedious or impractical with traditional load-pull. A modified nonlinear FET model is presented in this work that allows characterization of both thermal and trapping effects. New parameters and equation terms providing a trapping-related quiescent-bias dependence have been added to a popular nonlinear ("Angelov") model. A systematic method for fitting the quiescent-dependence parameters, temperature coefficients, and thermal resistance is presented, using a GaN high electron-mobility transistor as an example. The thermal resistance providing a good fit in the modeling procedure is shown to correspond well with infrared measurement results.

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Due to the current research needs and the lack of commercial multi-channel, multi-constellation GNSS receivers, a two-board solution has been developed so it can be mated with and take advantage of the processing power of the FPGA board branded as MicroZed. In order to achieve the proposed goals, an initial phase for assessing and updating the older design, building, and testing of SiGe modules (including both the electronics and casings) has been carried out. The results included demonstrate performances at logging GPS-L1 data with similar C/N0 and AGC values as the previous versions of the modules and offering navigation solutions with accuracies of a few meters. Secondly, a first iteration and design proposal for the new generation receiver has been proposed for GPS and GLONASS L1 and L2, which has been manufactured and tested. Partial tests have been performed due to the flaws of the current revision of the MicroZed Board in regards to its communication peripherals, and the results have validated the receiver’s design provided certain modifications are considered for future iterations. Furthermore, voltage and frequency tests have provided results with an error of less than 7%, and signal tests have provided C/N0 values similar to those of the SiGe modules of around 47[dB-Hz] which will be a useful baseline for future iterations. Finally, a design proposal for an Interface Board used between the older NT1065_PMOD Board and other FPGA boards carrying the standardized FMC connectors has been added to the report and negotiations with manufacturers have been engaged.

Leaflet replacement in aortic valve repair (AVr) is associated with increased long-term repair failure. Hemodynamic performance and mechanical stress levels were investigated after porcine AVr with 5 types of clinically relevant replacement materials to ascertain which material(s) would be best suited for repair. Porcine aortic roots with intact aortic valves were placed in a left-heart simulator mounted with a high-speed camera for baseline valve assessment. Then, the non-coronary leaflet was excised and replaced with autologous porcine pericardium (APP), glutaraldehyde-fixed bovine pericardial patch (BPP; Synovis™), extracellular matrix scaffold (CorMatrix™), or collagen-impregnated Dacron (HEMASHIELD™). Hemodynamic parameters were measured over a range of cardiac outputs (2.5–6.5L/min) post-repair. Material properties of the above materials along with St. Jude Medical™ Pericardial Patch with EnCapTM Technology (SJM) were determined using pressurization experiments. Finite element models of the aortic valve and root complex were then constructed to verify the hemodynamic characteristics and determine leaflet stress levels. This study demonstrates that APP and SJM have the closest profiles to normal aortic valves; therefore, use of either replacement material may be best suited. Increased stresses found in BPP, HEMASHIELD™, and CorMatrix™ groups may be associated with late repair failure.

Leaflet replacement in aortic valve repair (AVr) is associated with increased long-term repair failure. Hemodynamic performance and mechanical stress levels were investigated after porcine AVr with 5 types of clinically relevant replacement materials to ascertain which material(s) would be best suited for repair. Porcine aortic roots with intact aortic valves were placed in a left-heart simulator mounted with a high-speed camera for baseline valve assessment. Then, the non-coronary leaflet was excised and replaced with autologous porcine pericardium (APP), glutaraldehyde-fixed bovine pericardial patch (BPP; Synovis™), extracellular matrix scaffold (CorMatrix™), or collagen-impregnated Dacron (HEMASHIELD™). Hemodynamic parameters were measured over a range of cardiac outputs (2.5–6.5L/min) post-repair. Material properties of the above materials along with St. Jude Medical™ Pericardial Patch with EnCapTM Technology (SJM) were determined using pressurization experiments. Finite element models of the aortic valve and root complex were then constructed to verify the hemodynamic characteristics and determine leaflet stress levels. This study demonstrates that APP and SJM have the closest profiles to normal aortic valves; therefore, use of either replacement material may be best suited. Increased stresses found in BPP, HEMASHIELD™, and CorMatrix™ groups may be associated with late repair failure.

The researcher investigated the management of multi-grade teaching for optimal learning in Gauteng West primary schools. Ten participants, including school principals, heads of departments and educators participated in individual and focus group interviews and in observation of multi-grade classroom contexts. Findings revealed that educators involved in multi-grade teaching feel overwhelmed by challenging work conditions pertaining to large learner numbers and a lack of adequate didactical resources. This is exacerbated by a lack of professional development by means of tailor-made training for multi-grade teaching and the presumption that educators teaching such classes must merely change the monograde teaching format of the curriculum themselves for applicable implementation in a multi-grade teaching context. This leaves educators socially, emotionally and professionally isolated. Recommendations include the involvement of seasoned educators with expert knowledge and experience of multi-grade teaching to present training sessions constituting advice and support to inexperienced educators involved in said teaching. / Die navorser het die bestuur van meergraadonderrig by laerskole in Wes-Gauteng vir optimale leer ondersoek. Afgesien van individuele en fokusgroeponderhoude met skoolhoofde, departementshoofde en opvoeders, is waarneming in meergraadklaskamers gedoen. Volgens die bevindings bemoeilik groot klasse en ʼn gebrek aan didaktiese hulpmiddels meergraadopvoeders se taak. Meergraadopvoeders voel hulle geensins opgewasse teen hierdie werksomstandighede nie. ʼn Gebrek aan opleiding in meergraadonderrig en die veronderstelling dat opvoeders die eengraadformaat van die kurrikulum in ʼn meergraadformaat kan omskakel, vererger sake. Opvoeders is van mening dat hulle maatskaplik, emosioneel en professioneel in die steek gelaat word. Daar word aanbeveel dat gesoute opvoeders met kennis van en ervaring in meergraadonderrig onervare opvoeders oplei en adviseer. / Monyakisisi o dirile dinyakisiso ka ga go ruta dikereiti tse fapanego go fihlelela bokgoni le tsebo tikologong ya go thekga dinyakwa tsa baithuti dikolong tsa phoraemari go la Gauteng Bodikela. Batseakarolo ba lesome, go akaretswa dihlogo tsa dikolo, dihlogo tsa dikgoro le barutisi ba tseere karolo ditherisanong ka botee le dihlopha tseo di nepisitswego gape le temogo dikemong tsa diphaposi tsa dikereiti tse di fapanego. Dikhwetso di utollotse gore barutisi bao ba rutago dikereiti tse fapanego ba imelwa ke maemo a modiro wo o nyakago gore ba ntshe bokgoni bja bona ka moka ka lebaka la dipalo tse ntsi tsa baithuti le tlhokego ya dithusi tsa thuto tse di lekanego. Se se thatafiswa ke tlhokego ya tlhabollo ya profesene ye ka go fa tlhahlo yeo e lebanego ya go ruta dikreiti tse fapanego le kgopolo ya go re barutisi bao ba rutago ba swanela go no fetola popego ya lenaneothuto la kereiti e tee ka bobona go re ba le dirise kemong ya go ruta dikereiti tse fapanego. Se se dira gore barutisi ba ikhwetse ba se na kgokagano le setshaba leagong, ba hloka bao ba ka llelago go bona le go se be le bao ba nago le kgahlego go profesene ya bona. Ditshisinyo di akaretsa go ba gona ga barutisi bao e lego kgale ba ruta ba nago le maitemogelo le botsebi go ruta dikereiti tse fapanego go hlagisa dipaka tsa tlhahlo tseo di fago maele le thuso go barutisi bao ba se nago maitemogelo. / Educational Management and Leadership / M. Ed. (Education Management)