As CMOS technologies advance to 22-nm dimensions and below, constructing analog circuits are difficult to design within permitted specifications. One of the reasons for this is a limit of voltage resolution. In this situation, time-mode processing is a technique that is believed to be well suited for solving many of these challenges. A primary advantage of this technique is the ability to achieve analog functions using digital logic structures. Time difference amplifiers (TDA) can be a key component to realize fine time solutions. TDA are an innovative method to improve the time resolution as well as the evolution of ADC. This thesis introduces a TDA that amplifies the input time difference between two signals by a fractional gain. The closed loop gain control system used in this work consists of a pseudo differential current starved delay element (PDCSDE) and a monotonic digitally controlled delay element (DCDE). By using these elements to create a delay chain and a control loop, the result is a stable fractional time difference gain (TD gain). The system was designed and simulated in 65nm process at 1.2V power supply. The measured results show that this TDA achieves a fractional TD gain offset lower than 1.3%, with supply variation of ±15%, and input range as wide as ±250ps. The new design was also more resilient to process, voltage and temperature (PVT) variations