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Analysis of high performance interconnect in SoC with distributed switches and multiple issue bus protocolsNarayanasetty, Bhargavi 26 July 2011 (has links)
In a System on a Chip (SoC), interconnect is the factor limiting Performance,
Power, Area and Schedule (PPAS). Distributed crossbar switches also called as
Switching Central Resources (SCR) are often used to implement high performance
interconnect in a SoC – Network on a Chip (NoC). Multiple issue bus protocols like AXI
(from ARM), VBUSM (from TI) are used in paths critical to the performance of the
whole chip. Experimental analysis of effects on PPAS by architectural modifications to
the SCRs is carried out, using synthesis tools and Texas Instruments (TI) in house power
estimation tools. The effects of scaling of SCR sizes are discussed in this report. These
results provide a quick means of estimation for architectural changes in the early design
phase. Apart from SCR design, the other major domain, which is a concern, is deadlocks.
Deadlocks are situations where the network resources are suspended waiting for each
other. In this report various kinds of deadlocks are classified and their respective mitigations in such networks are provided. These analyses are necessary to qualify
distributed SCR interconnect, which uses multiple issue protocols, across all scenarios of
transactions. The entire analysis in this report is carried out using a flagship product of
Texas Instruments. This ASIC SoC is a complex wireless base station developed in 2010-
2011, having 20 major cores. Since the parameters of crossbar switches with multiple
issue bus protocols are commonly used in SoCs across the semiconductor industry, this
reports provides us a strong basis for architectural/design selection and validation of all
such high performance device interconnects.
This report can be used as a seed for the development of an interface tool for
architects. For a given architecture, the tool suggests architectural modifications, and
reports deadlock situations. This new tool will aid architects to close design problems and
bring provide a competitive specification very early in the design cycle. A working
algorithm for the tool development is included in this report. / text
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