Cette thèse est une tentative vers la conception de la bande Ka émetteur-récepteur RF pour les réseaux de capteurs sans fil (WSN), pour lesquelles la consommation d'énergie, le coût et la taille sont des paramètres critiques. Au sens de la consommation d'énergie, un transmetteur RF est la partie la plus cruciale d'un nœud de capteur. Nous avons choisi STMicroelectronics 90nm global purpose (GP) pour atteindre la technologie CMOS à faible puissance, faible coût et de petite taille. Pour la première fois, nous avons introduit la bande Ka dans le context de WSN, a fin de bénéficier de l'immunité élevée du réseau et la petite taille antenne. Étant donné que la technologie que nous avons choisi et du kit associé fonderie de conception n'est pas pour la conception RF, nous avons été obligés de mettre au point un outil de conception individuelle pour la bande à ondes millimétriques. De cette façon, nous avons développé une solution simple et précise le modèle MOS transistor, comprenant charge et le modèle de capacité, modèle de bruit et le modèle complet des effets parasites. Nous avons proposé une nouvelle structure pour les inducteurs de la ligne de transmission et un modèle précis de RLGC a été développé pour la conception et la simulation de ces inducteurs. Et puis par la simulation de la pleine d'onde (full wave) électromagnétique dans le logiciel HFSS, nous avons extrait des parameters du modele d'incucteurs , et d'autres éléments passifs, telles que des pads RF et T-jonctions. Comme notre première expérience, nous avons conçu et optimisé une LNA à 30 GHz, en utilisant notre outil de conception. Le LNA conçu a été fabriqué dans STMicroelectronics 90nm global dans le processus de GP CMOS et a été mesurée dans le laboratoire IMEP. Les résultats des mesures montrent 10dB gain de puissance et de 4,8 dB figre bruit (noise figure) avec 4mW DC la consommation de puissance. Dans l'étape suivante, nous avons conçu et optimisé mieux 30GHz LNA. La simulation post-layout montre 13.9dB gain de puissance et 3.6d figre bruit, avec seulement 3 mW de consommation de puissance. Nous avons proposé un lien simple radio et un structure simple a ete presente pour le récepteur_émetteur. Dans le récepteur, nous avons utilisé la structure hétérodyne, ou dans la quelle nous avons utilise de l'idee de Mixer Harmonique paire et oscillateur couple, à surmonter de nombreux problèmes se pose en mm bande des ondes dans la technologie CMOS. Le Mixer a été conçu en utilisant les résultats d'analyse et de simulation dans le kit de conception de fonderie: 4dB gain de conversion et de 5,8 double side band figre de bruit avec 2.2Mw consommation de puissance, un excellent résultat en comparaison avec les œuvres similaires rapports comme IF Stage 2GHz qui a été conçu comme multi-slice-amplificateur de la chaîne de detection pour accroître (ugmenter)la performance du récepteur et d'atteindre plus faible consommation d'énergie. Enfin, le récepteur a été simulé dans MATLAB et--87dBm de sensibilité, 890KHz de bande passante, avec 6.65mW consommation d'énergie sont obtenus. L'émetteur a été conçu aussi simple que possible, en utilisant idée power oscillateur, délivrant 6mW puissance RF de l'antenne. L'émetteur a généralement les 25% de power efficacité qui est très bon résultat en comparaison avec les œuvres déclarées.

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

In modern telecommunication there is the demand of high data rates using wideband component design. FCC has introduced the UWB spectrum for high speed data communication. UWB systems have attracted the attention of researchers.  Six-port transmitters and receivers are strong candidates for UWB systems and research is being done on six-port modulators and demodulators. In this work an effort is made to compare the performance of conventional single-ended six-port transmitter and receiver with differential six-port transmitters and receivers.    In this thesis, single ended and differential six-port correlators are designed on 7.5 GHz using Agilent Inc. EDA tool ADS and their performance is evaluated. A new wide-band differential six-port correlator is implemented using rat-race couplers and double-sided parallel strip-line phase inverter. The designed six-port correlators are used for 8-PSK modulation and demodulation. For transmitter-receiver system, mixed analog-DSP designing is used. The integral components of the system are evaluated individually and behavioral modeling is used to evaluate the complete transmitter-receiver system. The single-ended and differential systems are evaluated for noise-figure, dynamic range, bit error rate and data rate.

Advances toward increased integration and complexity of radio frequency (RF) andmixed-signal integrated circuits reduce the effectiveness of contemporary testmethodologies and result in a rising cost of testing. The focus in this research is on thecircuit-level implementation of alternative test strategies for integrated wirelesstransceivers with the aim to lower test cost by eliminating the need for expensive RFequipment during production testing.The first circuit proposed in this thesis closes the signal path between the transmitterand receiver sections of integrated transceivers in test mode for bit error rate analysis atlow frequencies. Furthermore, the output power of this on-chip loopback block wasmade variable with the goal to allow gain and 1-dB compression point determination forthe RF front-end circuits with on-chip power detectors. The loopback block is intendedfor transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitterreceiveroffset frequency differences from 40MHz to 200MHz. The measuredattenuation range of the 0.052mm2 loopback circuit in 0.13µm CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that theattenuation range can be reduced to 11-27dB via optimizations.Another circuit presented in this thesis is a current generator for built-in testing ofimpedance-matched RF front-end circuits with current injection. Since this circuit hashigh output impedance (>1k up to 2.4GHz), it does not influence the input matchingnetwork of the low-noise amplifier (LNA) under test. A major advantage of the currentinjection method over the typical voltage-mode approach is that the built-in test canexpose fabrication defects in components of the matching network in addition to on-chipdevices. The current generator was employed together with two power detectors in arealization of a built-in test for a LNA with 14% layout area overhead in 0.13µm CMOStechnology (<1.5% for the 0.002mm2 current generator). The post-layout simulationresults showed that the LNA gain (S21) estimation with the external matching networkwas within 3.5% of the actual gain in the presence of process-voltage-temperaturevariations and power detector imprecision.

Continued improvements of transceiver systems-on-a-chip play a key role in the advancement of mobile telecommunication products as well as wireless systems in biomedical and remote sensing applications. This dissertation addresses the problems of escalating CMOS process variability and system complexity that diminish the reliability and testability of integrated systems, especially relating to the analog and mixed-signal blocks. The proposed design techniques and circuit-level attributes are aligned with current built-in testing and self-calibration trends for integrated transceivers. In this work, the main focus is on enhancing the performances of analog and mixed-signal blocks with digitally adjustable elements as well as with automatic analog tuning circuits, which are experimentally applied to conventional blocks in the receiver path in order to demonstrate the concepts. The use of digitally controllable elements to compensate for variations is exemplified with two circuits. First, a distortion cancellation method for baseband operational transconductance amplifiers is proposed that enables a third-order intermodulation (IM3) improvement of up to 22dB. Fabricated in a 0.13µm CMOS process with 1.2V supply, a transconductance-capacitor lowpass filter with the linearized amplifiers has a measured IM3 below -70dB (with 0.2V peak-to-peak input signal) and 54.5dB dynamic range over its 195MHz bandwidth. The second circuit is a 3-bit two-step quantizer with adjustable reference levels, which was designed and fabricated in 0.18µm CMOS technology as part of a continuous-time SigmaDelta analog-to-digital converter system. With 5mV resolution at a 400MHz sampling frequency, the quantizer's static power dissipation is 24mW and its die area is 0.4mm^2. An alternative to electrical power detectors is introduced by outlining a strategy for built-in testing of analog circuits with on-chip temperature sensors. Comparisons of an amplifier's measurement results at 1GHz with the measured DC voltage output of an on-chip temperature sensor show that the amplifier's power dissipation can be monitored and its 1-dB compression point can be estimated with less than 1dB error. The sensor has a tunable sensitivity up to 200mV/mW, a power detection range measured up to 16mW, and it occupies a die area of 0.012mm^2 in standard 0.18µm CMOS technology. Finally, an analog calibration technique is discussed to lessen the mismatch between transistors in the differential high-frequency signal path of analog CMOS circuits. The proposed methodology involves auxiliary transistors that sense the existing mismatch as part of a feedback loop for error minimization. It was assessed by performing statistical Monte Carlo simulations of a differential amplifier and a double-balanced mixer designed in CMOS technologies.

This dissertation presents system and circuit development of the low-power multi-gigabit CMOS demodulator using analog and mixed demodulation techniques. In addition, critical building blocks of the low-power analog quadrature front-ends are designed and implemented using 90 nm CMOS with a targeted compatibility to the traditional demodulator architecture. It exhibits an IF-to-baseband conversion gain of 25 dB with 1.8 GHz of baseband bandwidth and a dynamic range of 23 dB while consuming only 46 mW from a 1 V supply voltage. Several different demodulators using analog signal processor (ASP) are implemented: (1) an ultra-low power non-coherent ASK demodulator is measured to demodulate a maximum speed of 3 Gbps while consuming 32 mW from 1.8 V supply; (2) a mere addition of 7.5 mW to the aforementioned analog quadrature front-end enables a maximum speed of 2.5 Gbps non-coherent ASK demodulation with an improved minimum sensitivity of -38 dBm; (3) a robust coherent BPSK demodulator is shown to achieve a maximum speed of 3.5 Gbps based on the same analog quadrature front-end with only additional 7 mW. Furthermore, an innovative seamless handover mechanism between ASP and PLL is designed and implemented to improve the frequency acquisition time of the coherent BPSK demodulator. These demodulator designs have been proven to be feasible and are integrated in a 60 GHz wireless receiver. The system has been realized in a product prototype and used to stream HD video as well as transfer large multi-media files at multi-gigabit speed.

SiGe BiCMOS technology has many advantageous properties that, when leveraged, enable circuit design for extreme environments. This work will focus on designs targeted for space system avioinics platforms under the NASA ETDP program. The program specifications include operation under temperatures ranging from -180 C to +125 C and with radiation tolerance up to total ionizing dose of 100 krad with built-in single-event latch-up tolerance. To the author's knowledge, this work presents the first design and measurement of a wide temperature range enabled, radiation tolerant as built, RS-485 wireline transceiver in SiGe BiCMOS technology. This work also includes design and testing of a charge amplification channel front-end intended to act as the interface between a piezoelectric sensor and an ADC. An additional feature is the design and testing of a 50 Ohm output buffer utilized for testing of components in a lab setting.

Submitted by Maria Suzana Diniz (msuzanad@hotmail.com) on 2015-11-05T14:36:51Z No. of bitstreams: 1 arquivototal.pdf: 4812802 bytes, checksum: e5276e62e6294058de196c6252bedc95 (MD5) / Made available in DSpace on 2015-11-05T14:36:51Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 4812802 bytes, checksum: e5276e62e6294058de196c6252bedc95 (MD5) Previous issue date: 2015-02-27 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - CAPES / This work deals with the evaluation of the communication system by radio frequency using the NRF-24L01+® transceiver to be used in monitoring of electrical systems on the concept of smart grid. The complete system consists of one or more Units Remote Data Acquisition - URDAs; multiple Smart Sensing Units - SSUs; and Supervisory Control Subsystem - SCS. The connection between URAD and SSUs may occur via wired connection (Ethernet, RS232, USB, CAN or PLC) and wireless (RF). URADs fit to the acquisition, processing and communication of variables with low time constant while the USIs are primarily responsible for the acquisition of magnitudes with larger time constants (temperature, pressure, humidity, etc.). In this work, we focus on development and communication of SSUs. For these tests the units are of two types: a master unit, responsible for requesting data (wireless) and sending the SCS (Communication RS232, USB, CAN or RF); and a slave unit, which may account for the measured variables of interest to send to the master unit when requested. For wireless communication (RF), the transceiver nRF - 24L01+® from NORDICTM was used, because its processing characteristics and communication satisfactorily meet the needs and requirements of the project, which will be addressed in the course of this work. / O presente trabalho trata da avaliação do sistema de comunicação por meio de rádio-frequência utilizando o transceiver nRF-24L01+® para ser utilizado no monitoramento de sistemas elétricos no conceito de smart grid. O sistema completo é composto de uma ou mais Unidades Remotas de Aquisição de Dados – URADs; de várias Unidades de Sensoriamento Inteligente – USIs; e um Subsistema de Controle Supervisório – SCS. A conexão entre a URAD e as USIs pode ocorrer através de conexão cabeada (Ethernet, RS232, USB, CAN ou PLC) e sem fio (RF). Cabem às URADs a aquisição, processamento e comunicação das grandezas com pequena constante de tempo, enquanto que as USIs encarregam-se da aquisição de grandezas com constantes de tempo maiores (temperatura, pressão, umidade, etc.). Neste trabalho, tratamos do desenvolvimento e de testes de comunicação da USI. Para estes testes as unidades são de 2 tipos: uma unidade mestre, responsável pela requisição dos dados (sem fio) e pelo envio ao SCS (comunicação RS232, USB, CAN ou RF); e uma unidade escravo, que pode ser responsável pela medição de grandezas de interesse para envio à unidade mestre quando requisitada. Para a comunicação sem fio (RF), utilizou-se o transceptor nRF-24L01+® da NORDICTM, pois suas características de processamento e comunicação atendem satisfatoriamente às necessidades e exigências do projeto, que serão abordadas no transcurso deste trabalho.

Cílem této diplomové práce bylo navrhnout moduly určené k demonstraci a testování některých obvodů, používaných v automobilové technice. Jedná se o LIN transceiver NCV7420 a osmivýstupový výkonový budič AMIS-39101. Návrh spočíval ve vybrání a popisu parametrů vhodných podpůrných obvodů, vytvoření celkového schématu a navržení desky plošných spojů tohoto modulu s ohledem na kompaktní rozměry a předpokládané testy. Dalším krokem byla tvorba firmware řídicího mikrokontroléru (C8051F344), jež zajišťuje LIN komunikaci, řízení budiče a základní monitorovací funkce. Poslední část popisuje software pro hostitelský PC umožňující komfortní řízení sítě složené z těchto modulů. Pro úplnost byl tento projekt doplněn o přehled vlastností sběrnice LIN a metodiky testování LIN transceiveru z hlediska funkčních parametrů i některých EMC měření. V příloha obsahuje kompletní schéma modulu, výkresy desek plošných spojů, seznam řídicích příkazů a fotografie modulu.

The aim of this master’s thesis is to design a device for identification of bus stops for blind people. In the beginning the work describes information about the RFID system, characterizes each part of this system, mutual communication of its components and evaluates possibilities of RFID communication frequency bands. Subsequently the work describes the block diagram of the device and the circuit scheme of each block. Work concentrates on a selection of circuit components for the RFID transceiver, the voice module, the control module and choose a suitable transponder to place it on metal constructions. Control programs are also described. PCB design of each board, partlists and source codes are in the appendices of this master’s thesis.