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REDUCING MEMORY SPACE FOR COMPLETELY UNROLLED LU FACTORIZATION OF SPARSE MATRICESTHIYAGARAJAN, SANJEEV 11 October 2001 (has links)
No description available.
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Aplicação de Loop Pipelining e Loop Unrolling à síntese de alto nívelFerrari, Dione Jonathan January 2002 (has links)
Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Ciência da Computação. / Made available in DSpace on 2012-10-20T09:40:08Z (GMT). No. of bitstreams: 1
188157.pdf: 431174 bytes, checksum: 32f4521af19e9fdd365fc47b62c259a6 (MD5) / Este trabalho tem como objetivo resolver um problema clássico da Síntese de Alto Nível através de uma abordagem orientada à exploração de soluções alternativas. O problema consiste no escalonamento de operações de um dado algoritmo sob restrição de recursos físicos de forma que cada operação é executada respeitando a ordem de precedência imposta pelo algoritmo. Para abordar o problema acima, utilizou-se as técnicas de Loop Pipelining e Loop Unrolling, onde operações de diferentes iterações podem ser executadas em um mesmo estado. Estas técnicas, por exporem mais paralelismo, permitem uma melhor utilização dos recursos. Este trabalho descreve a abordagem proposta, a modelagem que a ampara e a implementação de ferramentas que a suportam (escalonador e paralelizador). São apresentados resultados experimentais obtidos a partir de exemplos clássicos da literatura.
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A Hardware Interpreter for Sparse Matrix LU FactorizationSyed, Akber 16 September 2002 (has links)
No description available.
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Optimal Loop Unrolling for GPGPU ProgramsSreenivasa Murthy, Giridhar 30 September 2009 (has links)
No description available.
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Energy Efficient Loop Unrolling for Low-Cost FPGAsDumpala, Naveen Kumar 27 October 2017 (has links) (PDF)
Many embedded applications implement block ciphers and sorting and searching algorithms which use multiple loop iterations for computation. These applications often demand low power operation. The power consumption of designs varies with the implementation choices made by designers. The sequential implementation of loop operations consumes minimal area, but latency and clock power are high. Alternatively, loop unrolling causes high glitch power. In this work, we propose a low area overhead approach for unrolling loop iterations that exhibits reduced glitch power. A latch based glitch filter is introduced that reduces the propagation of glitches from one iteration to next. We explore the optimal number of filters to be inserted for different applications that give a good balance between area and power. We also implement partial unrolling with glitch filters. This approach consumes less area while still giving energy savings comparable to the fully unrolled implementation.
Our approach is targeted to Xilinx and Altera FPGAs. We simulate different implementation choices and compare energy results to evaluate the savings. We demonstrate our approach on SIMON-128 and AES-256 block ciphers and a sorting algorithm. We prototype our design on Xilinx Artix-7 and Altera Cyclone-IV-GX FPGA development boards and measure the actual power savings. Results show up-to 90% dynamic energy reduction in Xilinx designs, and 97% reduction in Altera designs with our glitch filtering approach due to glitch power reduction.
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