The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.