Field-programmable gate arrays (FPGAs) are excellent devices for high-performance computing, system-on-chip realization, and rapid system prototyping. While FPGAs offer flexibility and performance, they continue to lag behind application specific integrated circuit (ASIC) performance and power consumption. As manufacturing technology improves and IC feature size decreases, FPGAs may further lag behind ASICs due to interconnection scalability issues. To improve FPGA scalability, this thesis proposes an architectural enhancement to improve global communications in large FPGAs, where chip-length programmable interconnects are slow. It is expected that this architectural enhancement, based on wire emulation techniques, can reduce chip-length communication latency and routing congestion. A prototype wire emulation system that uses FPGA self-reconfiguration as a non-traditional means of intra-FPGA communication is implemented and verified on a Xilinx Virtex-II XC2V1000 FPGA. Wire emulation benefits and impact to FPGA architecture are examined with quantitative and qualitative analysis. / Master of Science

In the realm of FPGAs, many tool vendors offer behaviorally-based simulators aimed at easing the complexity of large FPGA designs. At times, a behaviorally-modeled design does not work in hardware as expected or intended. VTsim, a Virtex-II device simulator, was designed to resolve this and many other design problems by providing a window into the FPGA fabric via a virtual device. VTsim is an event-driven device simulator modeled at the CLB level with multiple clock domain support. Utilizing JBits3 and ADB, VTsim enables simulation and examination of all resources within an FPGA via a virtual device. The only input required by VTsim is a bitstream, which can be generated from any tool suite. The simulator is part of the JHDLBits open-source project, and was designed for rapid response, low memory usage, and ease of interaction. / Master of Science

In recent years, multi-core processors and multi-processor networks have grown in popularity as a solution to the limits on increasing clock speed, rising power consumption, and the nanometer manufacturing processes. Multi-core processors and multi-processor networks are seen as the next step in the advancement of computational capabilities by way of concurrent processing. However, parallel software design is difficult due to the immaturity of scalable architectures and software development environments for multi-core hardware. How should processors effectively and quickly pass information, with as little overhead as possible? What kind of communication architecture is best suited for parallelism? How can large-scale architectures be quickly produced, verified and properly utilized by software? Using commercially available FPGA development boards, Xilinx tools and components, this thesis offers a light-weight solution to these questions for effective, low-overhead, low-latency multi-core communication and fast prototyping of multi-processor networks for scalable processor arrays. / Master of Science

Orientador: Luis Geraldo Pedroso Meloni / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-14T05:58:36Z (GMT). No. of bitstreams: 1 LemesFilho_JoseMatias.pdf: 2987431 bytes, checksum: 93fc757a06215b93a08427d2f33f88a2 (MD5) Previous issue date: 2009 / Resumo: Este trabalho descreve o estudo, a pesquisa e compilação de técnicas de otimização de códigos em FPGA (Field Programmable Gate Arrays) utilizando uma ferramenta de prototipagem rápida. Para isso, foram implementados alguns algoritmos para auxiliar na apresentação e avaliação de quatro técnicas de otimização: uso de recursos alternativos, multiplexação no tempo, algoritmos alternativos e mudança da freqüência sistêmica. As principais contribuições do presente trabalho foram: compilar em um único documento diversas técnicas para geração eficiente de códigos de processamento digital de sinais; o estudo das etapas de fluxo de projeto baseado em ferramentas de prototipagem rápida; implementações de diversos algoritmos para demonstrar as técnicas de otimização, visando-se o estudo da minimização da área de ocupação em FPGA. Com o uso das técnicas pode-se alcançar uma redução de área da FPGA de até 90%, conforme a complexidade do sistema alvo. / Abstract: This work describes the study, research and compilation of programming optimization techniques for FPGA (Field Programmable Gate Arrays) using a tool technology for rapid prototyping. For this purpose, some algorithms have been implemented to help the presentation and evaluation of four optimization techniques: alternative resources usage, time multiplexing, alternative algorithms and systemic frequency change. The main contributions of this work are: compilation in one document several efficient techniques for generation code in digital signal processing; study of the phases of design flow were based on rapid prototyping tools; implementations of several algorithms to demonstrate the optimization techniques, looking for the minimization of the FPGA occupation area. With the use of these techniques, it is possible to reach a FPGA area reduction of up to 90%, depending of the complexity of the target system. / Universidade Estadual de Campi / Telecomunicações e Telemática / Mestre em Engenharia Elétrica

This project deals with computation of eigenvalues and eigenvectors of Hermitian positive-semidefinite complex square matrix of order 4. The target is an implementation of computation in language VHDL to field-programmable gate array of type Xilinx Zynq-7000. This master project deals with algorithms used for computation of eigenvalues and eigenvectors of positive-semidefinite symmetric real square and positive-semidefinite complex Hermitian matrix and the analysis of algorithms by AnalyzeAlgorithm program assembled for this purpose. The closing part of this project describes implementation of the computation into field-programmable gate array with use of IP core Xilinx® Floating-Point \linebreak Operator and SVAOptimalizer, SVAInterpreter and SVAToDSPCompiler programs.

The project is about embedded systems in self-driving vehicles which is a growing andcurrent area. This is important as the automation of vehicles can make different sectorssuch as the mining and logistics industry more effective. This work relates to the topicas it aims to improve part of the self-driving software stack by replacing Ubuntu with aless resource-intensive Linux based system. The main goal of this work is to implementand document improvements. The work contains a research part where advantages anddisadvantages are compared against each other, followed by an implementation thatiteratively solved one problem at a time.The result became instructions and documentation describing the choices madefor a less resource demanding Linux based system. It also includes instructions anddocumentation for two different application that are part of the software stack. / Projektet handlar om inbyggda system i självkörande fordon vilket är ett växande ochaktuellt område. Det är viktigt då automatiseringen av fordon kan effektivisera mångaolika sektorer som till exempel gruv- och logistikindustrin. Detta arbete relaterar tillämnet då det har som mål att effektivisera en del av den självkörande mjukvarustackengenom att byta ut Ubuntu till ett mindre resurskrävande Linux-system. Huvudmålet meddetta arbete är att implementera och dokumentera förbättringar. Arbetet innehåller en ut-redningsdel där för- och nackdelar jämförs mot varandra följt av en implementationsdelsom iterativt hanterar ett problem i taget.Resultatet blev instruktioner och dokumentation över de val som tagits för ett mindreresurskrävande Linux-system samt instruktioner och dokumentation över två applikatio-ner som är en del av mjukvarustacken.

FPGA based systems have been heavily used to prototype and test Application Specic Integrated Circuit (ASIC) designs with much lower costs and development time compared to hardwired prototypes. In recentyears, thanks to both the latest technology nodes and a change in the architecture of reconfigurable integrated circuits (from traditional Complex Programmable Logic Device (CPLD) to full-CMOS FPGA), FPGAs have become more popular in embedded systems, both as main computation resources and as hardware accelerators. A new era is beginning for FPGA based systems: the partial run-time reconguration of a FPGA is a feature now available in products already on the market and hardware designers and software developers have to exploit this capability. Previous works show that, when designed properly, a system can improve both its power efficiency and its performance taking advantage of a partial run-time reconfigurable architecture. Unfortunately, taking advantage of run-time reconfigurable hardware is very challenging and there are several problems to face: the reconfiguration overhead is not negligible compared to nowadays CPUs performance,the reconfiguration time is not easily predictable, and the software has to be re-though to work with a time-evolving platform. This thesis project aims to investigate the performance of a modern run-time reconfigurable SoC (a Xilinx Zynq 7020), focusing on the reconfiguration overhead and its predictability, on the achievable speedup, and the trade-off and limits of this kind of platform. Since it is not always obvious when an application (especially a real-time one) is really able to use at its own advantage a partial run-time reconfigurable platform, the data collected during this project could be a valid help for hardware designers that use reconfigurable computing. / FPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.

It is widely recognised that security is a concern in the design of a wide range of embedded systems. However, security for embedded systems remains an unsolved problem, which could create greater challenges in the future than security for mainstream computers today. The promise of universal connectivity for embedded systems creates increased possibilities for malicious users to gain unauthorised access to sensitive information. All modern security protocols use private-key and public-key algorithms. This thesis investigates three important cryptography algorithms (RC4, AES, and RSA) and their relevance to networked embedded systems. Limitations in processing power, battery life, communication bandwidth, memory and costs constrain the applicability of existing cryptography standards for small embedded devices. A mismatch between wide arithmetic for security (32 bit word operations) and embedded data bus widths (often only 8 or 16 bits) combined with a lack of certain operations (e. g., multi precision arithmetic) highlight a gap in the domain of networked embedded systems security. The aim of this thesis is to find feasible security solutions for networked embedded system applications. The above mentioned cryptography algorithms have been ported to three hardware platforms (Rabbit RCM3000, Xilinx Virtex 4 FPGA with MicroBlaze softcore, and a Linux desktop machine) in order to simulate several real world scenarios. Three applications – bidirectional transmission with encryption and decryption for various payload length, unidirectional transmission with very short payload, and encrypted data streaming – were developed to meet the simulation requirements. Several timing results were collected and used for calculating the achieved throughput. The Rabbit hardware platform, which represents the lower end in this thesis, was able to perform the RC4 crypto algorithm with a throughput of about 155 kbit/s. Thus the RC4 crypto algorithm was proven to outperform the AES crypto algorithm by a factor of 5, with AES achieving a throughput of about 32 kbit/s with the same hardware platform. The throughput was similar with the streaming application and UDP data transport. Without performing a cryto algorithm, the streaming application was able to process up to 1.5 Mbit/s. RSA was not implemented on the Rabbit hardware platform. The MicroBlaze hardware platform outperformed the Rabbit system by a factor of 5 – 10. It reached a throughput up to 1.5 Mbit/s with RC4 and up to 130 kbit/s with AES. The RSA algorithm reached up to 0.8 kbit/s on this hardware platform, showing that public-key ciphers are only suitable for short payload data, such as the exchange of a session key. The Linux machine was included in this test only to provide a reference to a non embedded system. The Linux performance was better than the MicroBlaze system by a factor of between 67 – 770, and better than the Rabbit platform by a factor of between 645 – 3125. Both the RC4 and the AES crypto algorithm reached a throughput of up to 100 Mbit/s on the Linux machine, with a throughput of up to 130 kbit/s reached with RSA. Hence, the Rabbit platform combined with the RC4 algorithm is suitable, for example, for MP3 streams with up to 150 kbit/s. The Rabbit platform with the AES algorithm could be used for low quality audio streams, for example for speech announcements. If a higher throughput is required, for example for video streams, the MicroBlaze could be an appropriate platform with throughput of up to 1.5 Mbit/s. Low cost embedded systems like Atmel AVR are not suitable for processing cipher algorithms developed in C. It is widely recommended that assembly language is used to develop such platforms.

This work describes using High-Level Synthesis in image processing application. The application is for Xilinx ZYNQ platform. The source code of components for FPGA is written in C++ programming language. For High-Level Synthesis is used Xilinx Vivado HLS tool. In the application are designed and implemented Sobel filter, Median filter, Bilateral filter and architecture for AdaBoost classificator. The extension of this work is implemented the component for network traffic. The component finds the begin of the packet.

This thesis contains introduction to PMS motor control using development board ZedBoard with Xilinx Zynq-7000 SoC. After that, there is a description of development environment Vivado and other modules. Finally, it contains description or created modules in Vivado environment which were combined together with peripheral drivers to demonstrate field oriented motor control algorithm of small PMS motor.