博士 / 國立交通大學 / 電子研究所 / 98 / Due to the trend of more and more SoC and SiP projects, the complication in chip, package and board designs, and signal interactions thereof is increasing very rapidly. Typical peripheral wire-bond design will be inappropriate for most modern designs; therefore flip-chip package becomes an inevitable choice. However, engineers usually designate the key interfaces including I/Os, bumps and package pin-out (ballplan) by hands in conventional flip-chip designs. The chip-package-board co-planning process is indeed time-consuming and always postpones the time-to-market (TTM) of products. In response to the aforementioned issues, this dissertation proposes methodologies in planning those interfaces with concurrent codesign paradigm, thus speeding up the developing time dramatically.
The dissertation contains three parts. First, we propose a novel and very efficient approach to automating pin-out designation in flip-chip BGA packaging for package-board codesign. The manual time-consuming codesign works can be replaced by proposed methodologies. Through considering signal integrity, power delivery, and routability in pin-block design, our frameworks provide trade-offs in signal performance and package cost while achieving the minimum package size. Second, we present a planning algorithm to optimize pin-block locations by using a new representation for pin-block placement, and defining range constraints in stochastic framework. The experimental results show that our algorithm optimizes the system interconnects during package pin-out planning. In addition to the package-board codesign, we develop a concurrent design flow for chip-package codesign in the third part. Comparing with the previous works, the methods in this part preliminarily provide the optimization study of net crossing and length deviation which are very critical requirements in chip-package codesign. By designing specific I/O-bump tiles and proposing an innovative I/O-row based scheme, two heuristic methods and one assignment algorithm are provided for package-aware I/O-bump planning. As a result, a chip-package-board co-planning automation attempt is accomplished for optimizing performance and design cost simultaneously.
| Identifer | oai:union.ndltd.org:TW/098NCTU5428092 |
| Date | January 2010 |
| Creators | Lee, Ren-Jie, 李仁傑 |
| Contributors | Chen, Hung-Ming, 陳宏明 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | en_US |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 95 |
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