碩士 / 國立交通大學 / 電子研究所 / 98 / IEEE 802.16e is a recently proposed standard for high speed wireless transmission. Orthogonal Frequency Division Multiplexing (OFDM) and Multiple-input Multiple-output (MIMO) technical is adopted in 802.16e. OFDM is a kind of multi-carrier modulation and data are divided into several differential and orthogonal subcarriers. MIMO is a kind of transmission way with multiple transmitting antennas and multiple receiving antennas. In this thesis, we focus on sampling clock offset (SCO) of 802.16e and build a simulation platform using C language. This platform contains carrier frequency synchronization, timing synchronization and frequency domain channel estimation, and we simulate SCO effect on this platform. We propose two kinds of model to illustrate SCO effects proposes three architectures to compensate SCO on OFDM and MIMO system. Finally, we propose a memory-efficiency architecture for sampling clock offset compensation. This architecture reduces the usage of memory by 85 %. This architecture can perfectly compensate SCO effect when SCO value is below 20 ppm, and make the BER less than 0.01 when SCO value is 40 ppm. However, without compensation, under 20 and 40 ppm SCO, the BER is 0.15 and 0.36 respectively. Thus, the proposed memory-efficiency architecture for sampling clock offset compensation improves the BER of the system significantly.
| Identifer | oai:union.ndltd.org:TW/098NCTU5428094 |
| Date | January 2010 |
| Creators | 林運翔 |
| Contributors | 周世傑 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | en_US |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 54 |
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