碩士 / 國立交通大學 / 電信工程研究所 / 98 / Over-sampling ΣΔ ADCs are widely used in application-specific ICs due to their high dynamic range and low power consumption. Thanks to the advance CMOS processes and continuous-time (CT) analog filter technique, the popularity of CT ΣΔ ADCs has been growing recently. Due to the non-sampling loop filter, it is feasible to build high-resolution CT ΣΔ ADCs with a bandwidth up to MHz at the same time, leading to more power- and area-efficient ADCs.
In this thesis, a wide-bandwidth low-power CT ΣΔ modulator with 10 MHz signal bandwidth is implemented in TSMC 0.18 μm CMOS process. To realize such application scenario, the proposed CTSDM comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time derivator structure. The proposed CTSDM achieves above 74 dB SNDR (12 ENOB) over a 10 MHz signal band. The power dissipation is 36 mW from a 1.8 V supply and the energy per conversion is 235 fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.
| Identifer | oai:union.ndltd.org:TW/098NCTU5435040 |
| Date | January 2010 |
| Creators | Hong, Kuo-Che, 洪國哲 |
| Contributors | Chiueh, Herming, 闕河鳴 |
| Source Sets | National Digital Library of Theses and Dissertations in Taiwan |
| Language | en_US |
| Detected Language | English |
| Type | 學位論文 ; thesis |
| Format | 78 |
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