Zhou Lin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 50-53). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims and Contribution --- p.3 / Chapter 1.3 --- Thesis Overview --- p.4 / Chapter 2 --- Field-Programmable Gate Array and Routing Algorithm in VPR --- p.6 / Chapter 2.1 --- Commercially Available FPGAs --- p.6 / Chapter 2.2 --- FPGA Logic Block Architecture --- p.7 / Chapter 2.2.1 --- Logic Block Functionality vs. FPGA Area-Efficiency --- p.7 / Chapter 2.2.2 --- Logic Block Functionality vs. FPGA Delay-Performance --- p.7 / Chapter 2.2.3 --- Lookup Table-Based FPGAs --- p.8 / Chapter 2.3 --- FPGA Routing Architecture --- p.8 / Chapter 2.4 --- Design Parameters of FPGA Routing Architecture --- p.10 / Chapter 2.5 --- CAD for FPGAs --- p.10 / Chapter 2.5.1 --- Synthesis and Logic Block Packing --- p.11 / Chapter 2.5.2 --- Placement --- p.11 / Chapter 2.5.3 --- Routing --- p.12 / Chapter 2.5.4 --- Delay Modelling --- p.13 / Chapter 2.5.5 --- Timing Analysis --- p.13 / Chapter 2.6 --- FPGA Programming Technologies --- p.13 / Chapter 2.7 --- Routing Algorithm in VPR --- p.14 / Chapter 2.7.1 --- Pathfinder Negotiated Congestion Algorithm --- p.14 / Chapter 2.7.2 --- Routing Algorithm Used by VPR --- p.16 / Chapter 3 --- Connection-Switch Box Design --- p.17 / Chapter 3.1 --- Introduction --- p.17 / Chapter 3.2 --- Connection-Switch Box Design Algorithm --- p.19 / Chapter 3.2.1 --- Connection between Logic Pins and Tracks --- p.20 / Chapter 3.2.2 --- Connection between Pad Pins and Tracks --- p.25 / Chapter 3.3 --- Switch Number Comparisons --- p.26 / Chapter 3.4 --- Experimental Results --- p.29 / Chapter 3.5 --- Summary --- p.32 / Chapter 4 --- Optimal MST-Based Graph Algorithm on FPGA Segmenta- tion Design --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- MST-Based Graph Algorithm on FPGA Channel Segmentation Design --- p.39 / Chapter 4.2.1 --- Net Merging Problem of Row-Based FPGAs --- p.41 / Chapter 4.2.2 --- Extended Net Merging Problem of Symmetrical Array FPGAs --- p.44 / Chapter 4.3 --- Experimental Results --- p.46 / Chapter 4.4 --- Summary --- p.46 / Chapter 5 --- Conclusions --- p.48 / Bibliography --- p.50
| Identifer | oai:union.ndltd.org:cuhk.edu.hk/oai:cuhk-dr:cuhk_324690 |
| Date | January 2004 |
| Contributors | Zhou, Lin., Chinese University of Hong Kong Graduate School. Division of Computer Science and Engineering. |
| Source Sets | The Chinese University of Hong Kong |
| Language | English, Chinese |
| Detected Language | English |
| Type | Text, bibliography |
| Format | print, xii, 53 leaves : ill. ; 30 cm. |
| Rights | Use of this resource is governed by the terms and conditions of the Creative Commons “Attribution-NonCommercial-NoDerivatives 4.0 International” License (http://creativecommons.org/licenses/by-nc-nd/4.0/) |
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